EPM3512AQC208-2 vs EPM3512AQC208-7 比較
詳細な並列比較: EPM3512AQC208-2 メーカー: Altera および EPM3512AQC208-7 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Intel
EPM3512AQC208-7 - MAX 3000A CPLD, 512 Macrocells, 7.5ns, 208-PQFP | Intel
EPM3512AQC208-7 Nrnd仕様比較
| パラメータ | EPM3512AQC208-2 | EPM3512AQC208-7 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $18.75 | $41.72 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| User I/O Pins | 172 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Speed Grade | -2 | — |
| パッケージ | PQFP-208 (QC) | 208-Pin PQFP (FQFP, gull-wing) |
| Supply Voltage (Core) | 3.3 V | — |
| Output Drive Voltage | 2.5 V / 3.3 V programmable | — |
| Input Voltage Tolerance | 2.5 V / 3.3 V / 5.0 V | — |
| Process Technology | 0.30 µm EEPROM | CMOS EEPROM, 0.30 um |
| Program/Erase Endurance | 100 cycles (typical) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| User I/O Banks | 4 | — |
| 動作温度範囲 | Commercial (0C to +70C) | — |
| 実装タイプ | Surface Mount | — |
| RoHS ステータス | Non-compliant (legacy PQFP) | Compliant |
| Lead-Free | No (SnPb lead finish) | Yes |
| Security Bit | Yes (programmable) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 10,000 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Counter Frequency (fCNT) | — | 116.3 MHz |
| User I/Os | — | 172 |
| Logic Elements / LEs | — | N/A (CPLD macrocell architecture) |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Standards Supported | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) |
| 動作温度 | — | 0 C to +70 C (commercial) |
| Programming | — | In-System Programmable via JTAG (IEEE Std. 1532) |