LC4064B-5T48I vs LC4064B-5T48C Comparación
Comparación detallada lado a lado de LC4064B-5T48I por Lattice Semiconductor y LC4064B-5T48C por Lattice Semiconductor. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | LC4064B-5T48I | LC4064B-5T48C |
|---|---|---|
| Marca | Lattice Semiconductor | Lattice Semiconductor |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Activo |
| Product Type | SuperFAST high-density programmable logic device (CPLD) | — |
| Device Series | ispMACH 4000B | — |
| Number of Macrocells | 64 macrocells | — |
| Number of I/O | 32 I/O | — |
| Speed Grade | 5 ns | — |
| Programming Type | In-system programmable (ISP) | — |
| Supported Supply Voltages | 1.8 V, 2.5 V, and 3.3 V | 3.3 V, 2.5 V, and 1.8 V |
| Encapsulado | 48-LQFP (TQFP-48) | — |
| Tipo de montaje | Surface mount | Surface mount |
| Rango de temperatura de funcionamiento | -40 °C to +105 °C (junction temperature) | [DATA_NEEDED: operating temperature range] |
| Logic Family | ispMACH 4000B SuperFAST high-density PLD | SuperFAST high-density PLD family |
| Frecuencia de reloj máxima | [DATA_NEEDED: maximum clock frequency] | — |
| Corriente de alimentación | [DATA_NEEDED: supply current] | — |
| Output Drive Current | [DATA_NEEDED: output drive current] | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating ambient temperature range] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| REACH Status | [DATA_NEEDED: REACH status] | [DATA_NEEDED: REACH status] |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | [DATA_NEEDED: AEC-Q100 qualification status] |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | In-System Programmable SuperFAST High-Density PLD |
| Macrocell Count | — | 64 macrocells |
| Maximum Operating Frequency | — | 400 MHz |
| Propagation Delay | — | 2.5 ns |
| Configuration Method | — | In-system programmable |
| Global Clock Pins | — | Up to 4 pins |
| Clock Polarity Control | — | Programmable |
| Product-Term Outputs per Macrocell | — | Up to 80 PTs per output |
| Package Type | — | 48-pin TQFP |
| Recuento de pines | — | 48 pins |
| Programmable Logic Type | — | Complex programmable logic device (CPLD) |
| I/O Pin Count | — | [DATA_NEEDED: I/O pin count] |
| Configuration Memory | — | [DATA_NEEDED: configuration memory details] |