LC4064B-5T48I vs LC4064B-5T48C Perbandingan

Perbandingan bersamaan detil LC4064B-5T48I dari Lattice Semiconductor dan LC4064B-5T48C dari Lattice Semiconductor. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Lattice Semiconductor
LC4064B-5T48I LC4064B-5T48I - 64-Macrocell 5ns ISP CPLD | Lattice

LC4064B-5T48I - 64-Macrocell 5ns ISP CPLD | Lattice

LC4064B-5T48I ✓ Aktif
Lattice Semiconductor
LC4064B-5T48C LC4064B-5T48C - 64-Macrocell 400 MHz CPLD | Lattice

LC4064B-5T48C - 64-Macrocell 400 MHz CPLD | Lattice

LC4064B-5T48C ✓ Aktif

Perbandingan Spesifikasi

Parameter Umum LC4064B-5T48I LC4064B-5T48C
Merek Lattice Semiconductor Lattice Semiconductor
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Aktif Aktif
Product Type SuperFAST high-density programmable logic device (CPLD) —
Device Series ispMACH 4000B —
Number of Macrocells 64 macrocells —
Number of I/O 32 I/O —
Speed Grade 5 ns —
Programming Type In-system programmable (ISP) —
Supported Supply Voltages 1.8 V, 2.5 V, and 3.3 V 3.3 V, 2.5 V, and 1.8 V
Paket 48-LQFP (TQFP-48) —
Tipe Mounting Surface mount Surface mount
Rentang Suhu Kerja -40 °C to +105 °C (junction temperature) [DATA_NEEDED: operating temperature range]
Logic Family ispMACH 4000B SuperFAST high-density PLD SuperFAST high-density PLD family
Frekuensi Bawah Maximum [DATA_NEEDED: maximum clock frequency] —
Arus Pemuat [DATA_NEEDED: supply current] —
Output Drive Current [DATA_NEEDED: output drive current] —
Suhu Kerja [DATA_NEEDED: operating ambient temperature range] —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
REACH Status [DATA_NEEDED: REACH status] [DATA_NEEDED: REACH status]
AEC-Q100 Qualification [DATA_NEEDED: AEC-Q100 qualification] [DATA_NEEDED: AEC-Q100 qualification status]
Lead-Free Status [DATA_NEEDED: lead-free status] —
Device Type — In-System Programmable SuperFAST High-Density PLD
Macrocell Count — 64 macrocells
Maximum Operating Frequency — 400 MHz
Propagation Delay — 2.5 ns
Configuration Method — In-system programmable
Global Clock Pins — Up to 4 pins
Clock Polarity Control — Programmable
Product-Term Outputs per Macrocell — Up to 80 PTs per output
Package Type — 48-pin TQFP
Jumlah Pin — 48 pins
Programmable Logic Type — Complex programmable logic device (CPLD)
I/O Pin Count — [DATA_NEEDED: I/O pin count]
Configuration Memory — [DATA_NEEDED: configuration memory details]

Spek dan Sumber

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