LC4064B-5T48I vs LC4064B-5T48C Comparaison
Comparaison détaillée côte à côte de LC4064B-5T48I par Lattice Semiconductor et LC4064B-5T48C par Lattice Semiconductor. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | LC4064B-5T48I | LC4064B-5T48C |
|---|---|---|
| Marque | Lattice Semiconductor | Lattice Semiconductor |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Product Type | SuperFAST high-density programmable logic device (CPLD) | — |
| Device Series | ispMACH 4000B | — |
| Number of Macrocells | 64 macrocells | — |
| Number of I/O | 32 I/O | — |
| Speed Grade | 5 ns | — |
| Programming Type | In-system programmable (ISP) | — |
| Supported Supply Voltages | 1.8 V, 2.5 V, and 3.3 V | 3.3 V, 2.5 V, and 1.8 V |
| Boîtier | 48-LQFP (TQFP-48) | — |
| Type de montage | Surface mount | Surface mount |
| Plage de température de fonctionnement | -40 °C to +105 °C (junction temperature) | [DATA_NEEDED: operating temperature range] |
| Logic Family | ispMACH 4000B SuperFAST high-density PLD | SuperFAST high-density PLD family |
| Fréquence d'horloge maximale | [DATA_NEEDED: maximum clock frequency] | — |
| Courant d'alimentation | [DATA_NEEDED: supply current] | — |
| Output Drive Current | [DATA_NEEDED: output drive current] | — |
| Température de fonctionnement | [DATA_NEEDED: operating ambient temperature range] | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| REACH Status | [DATA_NEEDED: REACH status] | [DATA_NEEDED: REACH status] |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | [DATA_NEEDED: AEC-Q100 qualification status] |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | In-System Programmable SuperFAST High-Density PLD |
| Macrocell Count | — | 64 macrocells |
| Maximum Operating Frequency | — | 400 MHz |
| Propagation Delay | — | 2.5 ns |
| Configuration Method | — | In-system programmable |
| Global Clock Pins | — | Up to 4 pins |
| Clock Polarity Control | — | Programmable |
| Product-Term Outputs per Macrocell | — | Up to 80 PTs per output |
| Package Type | — | 48-pin TQFP |
| Nombre de broches | — | 48 pins |
| Programmable Logic Type | — | Complex programmable logic device (CPLD) |
| I/O Pin Count | — | [DATA_NEEDED: I/O pin count] |
| Configuration Memory | — | [DATA_NEEDED: configuration memory details] |