AT28C17-15PC - 16Kbit Parallel EEPROM, 150 ns, 28-PDIP | Microchip
N.º de pieza: AT28C17-15PC ✓ Activo| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $6.2 | $6,20 |
| 10 | $5.55 | $55,50 |
| 100 | $4.9 | $490,00 |
| 500 | $4.4 | $2.200,00 |
| 1.000 | $3.95 | $3.950,00 |
AT28C17-15PC Descripción general
What is a parallel EEPROM? A parallel EEPROM is a non-volatile memory device that provides byte-wide data access (typically 8 bits per read/write cycle) over a parallel bus, as opposed to serial EEPROMs (I2C/SPI/Microwire) that move data one bit at a time. Parallel EEPROMs sit in the system hierarchy as: parallel EEPROM -> non-volatile memory (NVM) -> memory IC -> integrated circuit -> semiconductor. They were widely adopted in 8-bit and 16-bit microprocessor systems before flash memory densities made serial interfaces practical for all but the smallest data sets.
Key features include fast read access (150 ns), self-timed byte write cycle of 1 ms typical, internal address and data latches, an internal control timer, automatic clear-before-write, direct microprocessor control, DATA POLLING, and a READY/BUSY handshake output. The device is manufactured on Atmel's reliable nonvolatile CMOS process and supports byte-write operations without external erase cycles, simplifying firmware routines on legacy MCU platforms.
From an architectural standpoint, the AT28C17 integrates charge-pump-based high-voltage generation on-chip for the floating-gate cells, eliminating the need for an external VPP programming supply. An internal control timer sequences the write cycle automatically, freeing the host CPU to perform other tasks. WRITE PROTECT (pin WP) hard-disables writes to the upper half of the array, and DATA POLLING on I/O7 lets software detect end-of-write without continuous polling of the BUSY signal.
Typical applications include microcontroller-based configuration parameter storage, industrial control firmware scratchpad, point-of-sale terminal non-volatile data logs, legacy 8085/Z80/8051 system memory expansion, and instrumentation calibration tables. The 28-PDIP through-hole package makes the part especially useful for prototype boards, repair replacements for vintage equipment, and educational lab environments where socketed parts are preferred.
When designing with this device, observe the 4.5 V minimum supply for reliable byte-write operation and provide proper decoupling (typically 0.1 uF) close to VCC. The READY/BUSY open-drain output requires a pull-up resistor to VCC if used with a wired-OR connection to interrupt logic or other status lines.
This page synthesizes distributor pricing, parallel-EEPROM drop-in alternatives (AT28C16 family, M28C16, X28C16), and practical design notes not found in a single place on the manufacturer datasheet.
Alternativas directas para AT28C17-15PC — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
AT28C17-15PU
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
AT28C17-20PC
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
AT28C16-15PC
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
M28C17-15
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
X28C16P-25
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
AT28C17-15PC Valores máximos y características eléctricas
| Tipo de memoria | EEPROM (Electrically Erasable and Programmable ROM), non-volatile |
| Tamaño de memoria | 16 Kbit (2,048 bytes) |
| Organización de memoria | 2,048 words x 8 bits (2K x 8) |
| Interfaz | Parallel |
| Read Access Time | 150 ns (max) |
| Byte Write Cycle Time | 1 ms (typical, self-timed) |
| Supply Voltage (VCC) | 4.5 V to 5.5 V |
| Rango de temperatura de funcionamiento | 0 C to +70 C (commercial grade) |
| Encapsulado | 28-PDIP (Plastic DIP, through-hole, JESD-30 R-PDIP-T28) |
| Recuento de pines | 28 |
| Write Protection | Hardware WP pin protects upper 4Kbit array |
| End-of-Write Indication | DATA POLLING on I/O7 and open-drain READY/BUSY |
| Tipo de montaje | Through-Hole (THT) |
| Nivel MSL | Not Applicable (through-hole device) |
Configuración de pines de AT28C17-15PC
| Pin 1 | NC — Not connected (per datasheet) |
| Pin 2 | A12 — No-connect on AT28C17 (2K x 8 device) |
| Pin 3 | A7 — Address input A7 |
| Pin 4 | A6 — Address input A6 |
| Pin 5 | A5 — Address input A5 |
| Pin 6 | A4 — Address input A4 |
| Pin 7 | A3 — Address input A3 |
| Pin 8 | A2 — Address input A2 |
| Pin 9 | A1 — Address input A1 |
| Pin 10 | A0 — Address input A0 |
| Pin 11 | I/O0 — Bidirectional data I/O 0 |
| Pin 12 | I/O1 — Bidirectional data I/O 1 |
| Pin 13 | I/O2 — Bidirectional data I/O 2 |
| Pin 14 | GND — Ground |
| Pin 15 | I/O3 — Bidirectional data I/O 3 |
| Pin 16 | I/O4 — Bidirectional data I/O 4 |
| Pin 17 | I/O5 — Bidirectional data I/O 5 |
| Pin 18 | I/O6 — Bidirectional data I/O 6 |
| Pin 19 | I/O7 — Bidirectional data I/O 7 / DATA POLLING |
| Pin 20 | CE — Chip Enable (active low) |
| Pin 21 | A10 — Address input A10 |
| Pin 22 | OE — Output Enable (active low) |
| Pin 23 | A11 — Address input A11 |
| Pin 24 | A9 — Address input A9 |
| Pin 25 | A8 — Address input A8 |
| Pin 26 | NC — Not connected (per datasheet) |
| Pin 27 | WP — Write Protect (active high) |
| Pin 28 | VCC — +5V supply (4.5V to 5.5V) |
Aplicaciones típicas
AT28C17-15PC es adecuado para 6 aplicacións: Configuration Parameter Storage on 8-bit Microcontrollers, Industrial Control Calibration and Setpoint Storage, Legacy Point-of-Sale Terminal Non-Volatile Memory, Repairs and Replacement in Vintage 8-bit Systems, Instrumentation Calibration and Measurement Tables, Educational Lab Memory Subsystems.
Configuration Parameter Storage on 8-bit Microcontrollers
The AT28C17-15PC stores factory calibration, runtime configuration, and user-selectable parameters on 8-bit microcontroller platforms (8051, 68HC11, Z80, PIC) that lack on-chip EEPROM or whose internal NVM has been burned out. With 16 Kbit (2K x 8) of byte-addressable storage and 150 ns access time, it satisfies the timing requirements of 12 MHz-16 MHz 8051/8085 cores. Placed on the external memory bus as a memory-mapped peripheral, the parallel interface delivers faster read-side latency than any I2C EEPROM, while on-chip write-charge-pump and self-timed byte-write keep the host CPU free during 1 ms write cycles. WRITE PROTECT (WP) hard-locks the upper array to protect bootloader-grade constants from accidental overwrite.
Recomendado
Industrial Control Calibration and Setpoint Storage
The AT28C17-15PC retains non-volatile calibration tables, PID gain setpoints, and trip thresholds inside PLCs, motor drivers, and process controllers. The 4.5 V to 5.5 V supply integrates cleanly with industrial 5 V logic rails, and the 28-PDIP through-hole package survives high-vibration environments far better than SOIC-8 alternatives. Each byte supports roughly 100,000 write cycles, sufficient for most field-installed setpoints that change infrequently; for high-write-throughput applications, the host can route writes through a wear-leveling routine that cycles the write pointer across the array.
Recomendado
Legacy Point-of-Sale Terminal Non-Volatile Memory
The AT28C17-15PC holds the non-volatile transaction log, terminal-ID, store number, and tamper-resistant counters in legacy point-of-sale terminals. The 150 ns read access delivers low-latency reads during boot and during transaction-history scrolling, while the parallel interface fits 8085-style address/data multiplexed buses natively without glue logic. The READY/BUSY open-drain output lets the host CPU interrupt on end-of-write instead of polling, and DATA POLLING on I/O7 adds a software fallback for write-completion detection in legacy BIOS routines.
Recomendado
Repairs and Replacement in Vintage 8-bit Systems
The AT28C17-15PC is a direct socket replacement for older Atmel-compatible 28-pin parallel EEPROMs and equivalent 2716/2732-style EPROMs on retrocomputing and restoration boards. The 28-PDIP package with 0.6 inch pin-row spacing is dimensionally drop-in compatible with the original 28-pin DIP socket on Apple II, TRS-80, CP/M, and early IBM-PC expansion cards, enabling restoration without board redesign. With 16 Kbit of storage and 5 V single-supply operation, it represents the lowest-effort replacement when an original boot ROM or NVRAM is suspected of cell degradation after decades of storage.
Recomendado
Instrumentation Calibration and Measurement Tables
The AT28C17-15PC stores factory-loaded calibration tables, sensor linearization lookups, and unit-conversion constants in handheld DMMs, bench multimeters, and oscilloscope front ends. Its 2 Kbyte capacity comfortably fits per-range gain trim, TC coefficients for thermocouple inputs, and 50/60 Hz true-RMS correction factors. The parallel interface lets the host processor read the calibration block in essentially one bus cycle per byte without I2C overhead, supporting single-shot ADC conversions in fast sweep-mode instrumentation.
Recomendado
Educational Lab Memory Subsystems
The AT28C17-15PC integrates naturally into EE/CE laboratory courses on computer architecture and embedded systems thanks to its socket-friendly 28-PDIP package and bus-exposed control signals. Course modules cover address-latching with 74373 latches, data-bus buffering with 74245 transceivers, timing analysis on the 150 ns access waveform, and self-timed write-protocol firmware. Students can hand-solder the device onto wire-wrap or breadboard prototypes without reflow equipment and gain hands-on experience with byte-write, chip-erase-before-write, and DATA POLLING semantics.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para AT28C17-15PC — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | AT28C17-15PU | AT28C17-20PC | AT28C16-15PC | M28C17-15 | X28C16P-25 |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | STMicroelectronics | Renesas |
| Package | 28-PDIP | 28-PDIP - same | 28-PDIP - same | 28-PDIP - same | 28-PDIP - same | 28-PDIP - same |
| Density | 16 Kbit (2K x 8) | 16 Kbit (2K x 8) | 16 Kbit (2K x 8) | 16 Kbit (2K x 8) | 16 Kbit (2K x 8) | 16 Kbit (2K x 8) |
| Read Access Time | 150 ns | 150 ns | 200 ns | 150 ns | 150 ns | 250 ns |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Interface | Parallel | Parallel | Parallel | Parallel | Parallel | Parallel |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C |
| Lead Finish | Pb-free (PC suffix) | Pb-free matte tin | Pb-free | Pb-free | Pb-free | Pb-free |
Diferenciadores clave
- Industry-standard 150 ns grade in 28-PDIP socket-compatible footprint (frente a M28C17-15 (STMicroelectronics))
- Lead-free (Pb-free) finish on the -PC suffix (frente a AT28C17-15PU)
- Fastest 2K x 8 parallel EEPROM grade available at this density (frente a X28C16P-25 (Renesas))
- Self-timed byte write with hardware end-of-write indicators (frente a AT28C16-15PC)
Notas de diseño
Place a 0.1 uF ceramic decoupling capacitor as close as possible to the VCC pin (pin 28) and a bulk tantalum or aluminum electrolytic (typically 10 uF) within 1 inch on the +5 V supply trace. The AT28C17-15PC draws brief transients during internal write-pump operation; without adequate decoupling the VCC rail can sag and corrupt the in-flight write cycle. Keep the GND return path short - tie pin 14 directly to the ground plane with a via right at the package pin.
Use a 74HC573 or 74LS573 latch between the multiplexed 8051 address/data bus and the AT28C17-15PC A0-A10 inputs, controlled by ALE falling edge. The 150 ns access time is sufficient to capture data after ALE with one wait state on most 8051 cores running at 12 MHz; at 16 MHz (60 ns bus cycle) insert one or two wait states via RD stretch. Leave address inputs > A10 floating or pulled to GND - they are no-connect on this 2 Kbyte device but the unused die cells internally decode them and floating pins may toggle spurious block writes if WP glitches.
Always drive CE (active low) to its high level when transitioning the bus from a read to a write cycle, then re-assert CE low to begin the new cycle. Failing to toggle CE can cause a double-write or corrupted byte because the AT28C17-15PC latches the write on the first CE falling edge after WE falling. Use DATA POLLING on I/O7 - after issuing a write, read the same address; I/O7 reflects the complement of the last written bit until the internal write completes (~1 ms), then flips to true data.
Route the READY/BUSY open-drain output to a host interrupt or status GPIO and pull up to VCC with 4.7 kohm to 10 kohm. Route the WP pin through a series 10 kohm resistor to the controlling logic so an out-of-spec MCU pin transient cannot latch the device into permanent write-protected mode without state visibility. For boards mixing 5 V EEPROMs with 3.3 V MCUs, level-shift the address and control lines (but not VCC) using 74HCT245 rather than 74HC245 to guarantee TTL-input thresholds.
Información de cumplimiento
RoHS, REACH, lead-free, halogen-free, and conflict-mineral compliance status was not specified in the verified web data. -PC suffix typically denotes Pb-free matte-tin lead finish on legacy Atmel products, but confirm against the manufacturer datasheet before claiming compliance for restricted-substance-sensitive designs. AEC-Q100 is not_applicable (this is a commercial-temperature 0 C to +70 C parallel EEPROM, not an automotive-grade part - consider AT28C17-15PU-Industrial or automotive-qualified equivalents for vehicle applications).
