MX7672K/D
MX7672K/D - 12-Bit 3µs SAR ADC, Die Form | Maxim Integrated
The Maxim Integrated (Analog Devices) MX7672K/D is a 12-bit, high-speed, BiCMOS successive-approximation analog-to-digital converter (ADC) supplied in unpackaged die form, performing a full conversion in as little as 3µs while consuming only 110 mW. The die-format /D suffix means the part is shipped as a bare die on a waffle pack or similar carrier for hybrid and MCM (multi-chip module) integration, rather than in a conventional plastic package. The device accepts a single analog input channel, uses an external -5 V reference, and includes a buffered reference input so one reference can drive multiple MX7672 ADCs simultaneously. The MX7672 is documented as a plug-in replacement for the AD7672, simplifying migration of legacy analog-to-digital subsystems onto Maxim/ADI silicon.
An SAR ADC (successive-approximation register analog-to-digital converter) is a type of data converter that performs a binary search against the analog input using an internal DAC and comparator, producing one bit per clock cycle. SAR ADCs sit inside the broader hierarchy of analog-to-digital converters (ADC) -> data converters -> data acquisition ICs -> signal chain -> mixed-signal semiconductors. They are valued for their deterministic latency, low power, and excellent DC accuracy, making them a workhorse for industrial process control, instrumentation, and precision data-acquisition front ends.
Key features of the MX7672 include 12-bit resolution with no missing codes, a 3µs typical conversion time (yielding roughly 308 kSPS throughput), an external -5 V reference input with buffer, a BiCMOS process for low-power high-speed operation, and a clock input that can be driven from a crystal or an external microprocessor clock. The architecture supports both unipolar (0 V to VREF) and bipolar (±VREF) input ranges when the device is paired with the appropriate input conditioning. The buffered reference minimizes reference-source loading and stabilizes conversion gain across temperature.
Architecturally the MX7672 uses a charge-redistribution DAC array and a low-noise comparator, clocked by an internal state machine that implements the SAR algorithm. The BiCMOS process merges bipolar transistors for the reference buffer, comparator, and analog front end with CMOS logic for the SAR register and digital interface, optimizing both analog accuracy and digital power. Power dissipation of 110 mW is competitive for a 12-bit 3µs SAR ADC of this generation, and the device scales power with the clock since the SAR core only burns current during the active conversion window.
Typical applications for the MX7672 include industrial process control loops, precision data-acquisition front ends, multi-channel instrumentation with external analog multiplexers, motor control feedback ADCs, weigh-scale and load-cell digitizers, hybrid/MCM signal-conditioning modules, and legacy drop-in upgrades for AD7672-based boards. The combination of high speed, low power, and single-supply-friendly operation makes it well-suited to dense multi-channel systems where one reference serves many converters.
When designing with the MX7672 in die form, plan the die layout, ESD protection, wire-bond interconnect, and package selection carefully — die-format parts require hermetic or custom packaging, bond-pad ESD protection, and substrate-bias management. Ensure the external -5 V reference is low-noise and well decoupled at the reference pin; the buffered reference input is forgiving but still benefits from a 10µF local bypass capacitor. Keep analog and digital grounds separated at the die assembly and join them at a single star point to preserve 12-bit accuracy.
This page synthesizes Maxim/ADI distributor pricing, same-package drop-in alternatives, hybrid/MCM design notes, and AD7672 migration guidance not found in the standalone manufacturer datasheet, providing an engineer-ready overview for selecting the MX7672K/D in legacy and new designs.
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