2EDN7534FXTMA1 vs 2EDN7524GXTMA1 Comparaison
Comparaison détaillée côte à côte de 2EDN7534FXTMA1 par Infineon et 2EDN7524GXTMA1 par Infineon. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Infineon
2EDN7524GXTMA1 - 5A Dual Low-Side Gate Driver for MOSFET/GaN | Infineon
2EDN7524GXTMA1 ✓ ActifComparaison des spécifications
| Paramètre | 2EDN7534FXTMA1 | 2EDN7524GXTMA1 |
|---|---|---|
| Marque | Infineon | Infineon |
| Catégorie | Power MOSFET Drivers | Power MOSFET Drivers |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,71 | $0,82 |
| Driver Type | Low-Side, Dual Channel | — |
| Number of Drivers | 2 | — |
| Peak Output Current | 5 A (source/sink) | — |
| Supply Voltage (VDD) | 4.5 V to 20 V | — |
| Input Voltage Range (logic pins) | -12 V to +22 V (absolute max) | — |
| Propagation Delay (typical) | 19 ns | — |
| Input Logic Compatibility | LV-TTL | — |
| Output Polarity | Non-Inverting | — |
| Output Voltage Clamping | Active, to VDD | — |
| Rise Time (typ.) | [DATA_NEEDED: rise time] | — |
| Fall Time (typ.) | [DATA_NEEDED: fall time] | — |
| Channel-to-Channel Skew | [DATA_NEEDED: channel skew] | — |
| Under-Voltage Lockout | Yes | — |
| Broche d'activation | Yes | — |
| Température de fonctionnement | -40C to +125C | -40 C to +125 C |
| Boîtier | PG-DSO-8 | PG-WSON-8-1 (3 mm x 3 mm) with exposed thermal pad |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | Compliant | Compliant |
| Product Type | — | Low-side gate driver IC |
| Number of Channels | — | 2 (dual) |
| Drive Current (Source/Sink) | — | 5 A peak |
| Input Logic | — | Non-inverting, TTL / 3.3 V CMOS-compatible |
| Input Voltage Tolerance | — | -10 V to +20 V on logic pins |
| Supply Voltage (VCC) | — | 4.5 V to 20 V [DATA_NEEDED: exact range] |
| Propagation Delay | — | 20 ns typical [DATA_NEEDED: exact figure] |
| Channel-to-Channel Delay Matching | — | 1 ns |
| Temps de montée | — | 5 ns typical [DATA_NEEDED: exact test condition] |
| Temps de descente | — | 5 ns typical [DATA_NEEDED: exact test condition] |
| Output Stage | — | Rail-to-rail, separate source/sink |
| UVLO Protection | — | Yes |
| Niveau MSL | — | [DATA_NEEDED: MSL level] |
| Target Devices | — | Standard MOSFETs, superjunction MOSFETs, GaN HEMTs |