EP3SE260H780C4L vs EP3SE260H780C3N Comparaison
Comparaison détaillée côte à côte de EP3SE260H780C4L par Intel et EP3SE260H780C3N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ ActifComparaison des spécifications
| Paramètre | EP3SE260H780C4L | EP3SE260H780C3N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 190,00 | $1 325,00 |
| Family | Stratix III E | — |
| Logic Elements | 255,000 | — |
| LABs/CLBs | 10,200 | — |
| Total RAM Bits | 16,672,768 (16.7 Mbit) | — |
| User I/O Count | 488 | — |
| Boîtier | 780-ball FCBGA (HBGA 33x33 mm) | 780-BBGA, FCBGA (H780) |
| Speed Grade | C4 (middle/slow tier) | — |
| Core Voltage | 0.9 V (nominal) | — |
| Température de jonction en fonctionnement | 0C to +85C (commercial) | — |
| Type de montage | Surface Mount (flip-chip BGA) | Surface Mount |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Statut RoHS | Compliant (lead-free per datasheet) | Compliant (lead-free 'N' suffix) |
| Transceivers | Up to 24 multi-gigabit transceivers | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| Memory Interface | DDR3, DDR2, QDRII+, RLDRAM II controllers | — |
| Configuration Mode | PS, FPP, JTAG with EPCS/EPCQ | — |
| Series | — | Stratix® III E |
| Logic Elements (LE) | — | 255,000 |
| Embedded Memory (bits) | — | 16,672,768 |
| Number of LABs/CLBs | — | 10,200 |
| User I/Os | — | 488 |
| Number of Pins / Balls | — | 780 |
| Température de fonctionnement | — | 0 °C to +85 °C (C grade, commercial) |
| Process Technology | — | 40 nm CMOS |
| Maximum Core Frequency | — | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks and precision] |
| Niveau de sensibilité à l'humidité (MSL) | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |