EPC2LC20ES vs EPC2LC20 Comparaison
Comparaison détaillée côte à côte de EPC2LC20ES par Intel et EPC2LC20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2LC20ES | EPC2LC20 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Actif | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $5,85 | $7,20 |
| Type de mémoire | Configuration PROM (Non-volatile) | Non-volatile configuration PROM |
| Taille de mémoire | 1.6 Mbit | 1.6 Mbit |
| Target Device | SRAM-based FPGAs and LUT devices | — |
| Interface | Serial (DCLK/DATA) with JTAG ISP | — |
| Operating Voltage | 3.3 V and 5.0 V tolerant | — |
| JTAG Standard | IEEE Std. 1149.1 compliant | — |
| In-System Programmability | Yes (via built-in JTAG) | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| Configuration Modes | Serial and parallel supported | — |
| Boîtier | 20-PLCC (J-lead, 9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Type de montage | Surface Mount / Through-Hole (PLCC socket) | Surface Mount |
| Nombre de broches | 20 | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Statut RoHS | Compliant (ES suffix denotes lead-free industrial) | Non-Compliant (original Altera Pb-containing part) |
| Programming Interface | JTAG (4-wire: TDI/TDO/TMS/TCK) | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Manufacturer | Intel (formerly Altera) | — |
| Configuration Interface | — | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |