EPC2LC20ES vs EPC2LC20 比較
詳細並排比較 EPC2LC20ES 由 Intel 與 EPC2LC20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LC20ES | EPC2LC20 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | 啟用中 | NRND |
| 單價 (USD) | — | $7.20 |
| 記憶體類型 | Configuration PROM (Non-volatile) | Non-volatile configuration PROM |
| 記憶體容量 | 1.6 Mbit | 1.6 Mbit |
| Target Device | SRAM-based FPGAs and LUT devices | — |
| 介面 | Serial (DCLK/DATA) with JTAG ISP | — |
| Operating Voltage | 3.3 V and 5.0 V tolerant | — |
| JTAG Standard | IEEE Std. 1149.1 compliant | — |
| In-System Programmability | Yes (via built-in JTAG) | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| Configuration Modes | Serial and parallel supported | — |
| 封裝 | 20-PLCC (J-lead, 9x9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| 安裝類型 | Surface Mount / Through-Hole (PLCC socket) | Surface Mount |
| 腳位數 | 20 | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| RoHS 狀態 | Compliant (ES suffix denotes lead-free industrial) | Non-Compliant (original Altera Pb-containing part) |
| Programming Interface | JTAG (4-wire: TDI/TDO/TMS/TCK) | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Manufacturer | Intel (formerly Altera) | — |
| Configuration Interface | — | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |