EPM3256ATI144-10N vs EPM3256ATI144-10 Comparaison
Comparaison détaillée côte à côte de EPM3256ATI144-10N par Altera et EPM3256ATI144-10 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM3256ATI144-10N | EPM3256ATI144-10 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,25 | $0,00 |
| Family | MAX 3000A | — |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macrocells | 256 | — |
| Usable Gates | 5,000 | — |
| User I/Os | 116 | — |
| Logic Blocks / Logic Elements | 16 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Max Frequency (fMAX) | 95.2 MHz | — |
| Supply Voltage - Core | 3.3 V | — |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V (multi-voltage) | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V mixed |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | — |
| Boundary-Scan Test (BST) | Yes, IEEE Std. 1149.1 (JTAG) | — |
| Boîtier | 144-pin TQFP | 144-pin TQFP (20x20 mm) |
| Température de fonctionnement | -40 C to +85 C (industrial, "I" suffix) | -40°C to +85°C (industrial) |
| Lead-Free / Pb-Free | Yes ("N" suffix) | — |
| Statut RoHS | Compliant | — |
| Process Technology | CMOS EEPROM-based, non-volatile | — |
| Type de montage | Surface Mount | Surface Mount |
| Niveau MSL | 3 (per JEDEC J-STD-020, typical for TQFP) | — |
| Series | — | MAX 3000A |
| Programmable Type | — | In-System Programmable (ISP), EEPROM-based |
| Number of Macrocells | — | 256 |
| Number of Logic Elements / Blocks | — | 16 LABs (Logic Array Blocks) |
| Number of Gates | — | 5,000 typical usable gates |
| Number of User I/O | — | 116 |
| Propagation Delay (tpd max) | — | 10 ns |
| Maximum Frequency (fmax) | — | 95.2 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V nominal) |
| Logic Family | — | CMOS, EEPROM-based |
| Programming Interface | — | JTAG (IEEE 1149.1) and IEEE Std. 1532 ISP |
| Compliance | — | IEEE Std. 1532 ISP, PCI-compatible I/O |
| Statut du cycle de vie | — | Obsolete (per HighqualityPCB listing) |