DSPIC33FJ128MC706A-E/MR - 40 MIPS 16-Bit DSC 128KB Flash | Microchip
Référence : DSPIC33FJ128MC706A-E/MR ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $11.4 | $11,40 |
| 10 | $10.26 | $102,60 |
| 100 | $9.1 | $910,00 |
| 500 | $8.45 | $4 225,00 |
| 1 000 | $7.6 | $7 600,00 |
DSPIC33FJ128MC706A-E/MR Présentation
A Digital Signal Controller (DSC) is a hybrid device that combines the interrupt-driven deterministic behaviour of a microcontroller with the high-throughput numeric capabilities of a Digital Signal Processor (DSP). Within the broader semiconductor taxonomy, this dsPIC33F part belongs to the DSC > MCU > microcontroller > embedded processor hierarchy and is purpose-built for closed-loop control applications where both fast math (PID, Clarke/Park transforms, FIR filters) and deterministic I/O handling must coexist on a single chip.
Key differentiating specifications include an integrated 6-channel 10-bit ADC with 1.1 Msps throughput, dedicated motor-control PWM modules with up to 8 outputs and complementary mode, quadrature encoder interface (QEI) hardware, and four serial I/O ports (UART/SPI/I2C) for sensor and communication interfacing. The 40 MIPS core executes a single-cycle 16x16-bit MAC in one instruction cycle, enabling deterministic sensorless motor control loops in software.
The architecture pairs a modified Harvard bus with a 16-bit native datapath and DSP-aware instructions (MAC, ED, EDAC). Hardware multiplier and barrel shifter remove the need for software emulation of these primitives. The device also integrates 11 timers (including five 16-bit and two 32-bit), four IC/OC/PWM channels, and a real-time clock, giving designers a complete control-oriented peripheral set without external glue logic.
Typical applications include brushless DC motor control, single- and three-phase AC induction motor drives, switched reluctance motor controllers, uninterruptible power supplies (UPS), and digital power conversion. The part's deterministic 40 MIPS performance makes it a workhorse for both consumer appliance drives and industrial variable-frequency drives.
When designing with this device, allocate the exposed pad (EP) to a continuous ground copper plane to meet thermal ratings (typical theta-JA for the 9x9 mm VQFN-EP64 package is approximately 28 C/W on a 4-layer JEDEC board). Use MPLAB X IDE with the XC16 compiler and the dsPIC DSP Library for FFT, PID, and motor-control primitive functions. The "-E" suffix denotes the extended operating temperature range (-40C to +125C).
This page synthesizes distributor pricing, parametric cross-references, and practical PCB-layout guidance specific to the 64-pin VQFN variant - information not assembled on any single manufacturer or distributor page.
Alternatives de remplacement direct pour DSPIC33FJ128MC706A-E/MR — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec DSPIC33FJ128MC706A-E/MR (même facteur de forme et même empreinte) — différant par Package, Core Architecture, Operating Temperature, Timers, Program Memory (Flash).
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
DSPIC33FJ128MC706A-I/MR
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$6.54 / unité
Voir la fiche technique →DSPIC33FJ128MC706AT-I/MR
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$5.4 / unité
Voir la fiche technique →DSPIC33FJ128MC706A-H/MR
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$6.48 / unité
Voir la fiche technique →DSPIC33FJ64MC706A-E/MR
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$5.2 / unité
Voir la fiche technique →DSPIC33FJ128MC506A-E/MR
✅ Remplacement direct✓ En stock
$4.82 / unité
Voir la fiche technique →DSPIC33FJ128MC506A-I/MR
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$4.42 / unité
Voir la fiche technique →DSPIC33FJ128MC706A-E/MR Valeurs maximales et caractéristiques électriques
| Core Architecture | dsPIC33F 16-bit DSC (modified Harvard, DSP engine) |
| Maximum CPU Speed | 40 MIPS (40 MHz) |
| Program Memory (Flash) | 128 KB |
| Data RAM | 16 KB |
| DMA Channels | 8 channels |
| ADC | 10-bit, up to 1.1 Msps, 6 channels |
| Motor Control PWM | 8 outputs, complementary mode, dedicated PWM module |
| Quadrature Encoder Interface (QEI) | Yes, 1 module |
| Timers | 11 (5x 16-bit, 2x 32-bit, plus time base) |
| Serial I/O | 4 (UART / SPI / I2C configurable) |
| Input Capture / Output Compare / PWM | 4 channels |
| Operating Voltage | 3.0 V to 3.6 V |
| Température de fonctionnement | -40 C to +125 C (extended, "-E" suffix) |
| Boîtier | 64-pin VQFN (9x9 mm) with exposed pad |
| Type de montage | Surface Mount |
| Statut RoHS | Compliant |
| Lead-Free / Halogen-Free | Yes |
Configuration des broches de DSPIC33FJ128MC706A-E/MR
| Broche 1 | RP15/PWM1H/RE5 — Remappable I/O / PWM1H output / bus RE5 |
| Broche 2 | RP14/PWM1L/RE4 — Remappable I/O / PWM1L output / bus RE4 |
| Broche 3 | RP13/PWM2H/RE3 — Remappable I/O / PWM2H output / bus RE3 |
| Broche 4 | RP12/PWM2L/RE2 — Remappable I/O / PWM2L output / bus RE2 |
| Broche 5 | RP11/PWM3H/RE1 — Remappable I/O / PWM3H output / bus RE1 |
| Broche 6 | RP10/PWM3L/RE0 — Remappable I/O / PWM3L output / bus RE0 |
| Broche 7 | AVDD — Analog supply (+3.3 V) |
| Broche 8 | AVSS — Analog ground |
| Broche 9 | AN0/RP0 — ADC analog input 0 / remappable I/O RP0 |
| Broche 10 | AN1/RP1 — ADC analog input 1 / remappable I/O RP1 |
| Broche 11 | AN2/RP2 — ADC analog input 2 / remappable I/O RP2 |
| Broche 12 | AN3/RP3 — ADC analog input 3 / remappable I/O RP3 |
| Broche 13 | AN4/RP4 — ADC analog input 4 / remappable I/O RP4 |
| Broche 14 | AN5/RP5 — ADC analog input 5 / remappable I/O RP5 |
| Broche 15 | VDD — Digital supply (+3.3 V) |
| Broche 16 | VSS — Digital ground |
| Broche 17 | OSC1/RC12 — Crystal oscillator input / remappable I/O |
| Broche 18 | OSC2/RC15 — Crystal oscillator output / remappable I/O |
| Broche 19 | MCLR — Master Clear reset (active-low) |
| Broche 20 | PGEC1 — ICSP programming clock 1 |
| Broche 21 | PGED1 — ICSP programming data 1 |
| Broche 22 | PGEC2 — ICSP programming clock 2 |
| Broche 23 | PGED2 — ICSP programming data 2 |
| Broche 24 | RP6/RC1 — Remappable I/O RP6 / bus RC1 |
| Broche 25 | RP7/RC2 — Remappable I/O RP7 / bus RC2 |
| Broche 26 | RP8/RC3 — Remappable I/O RP8 / bus RC3 |
| Broche 27 | RP9/RC4 — Remappable I/O RP9 / bus RC4 |
| Broche 28 | VDD — Digital supply (+3.3 V) |
| Broche 29 | VSS — Digital ground |
| Broche 30 | PWM4H/RD1 — PWM4H output / bus RD1 |
| Broche 31 | PWM4L/RD2 — PWM4L output / bus RD2 |
| Broche 32 | PWM5H/RD3 — PWM5H output / bus RD3 |
| Broche 33 | PWM5L/RD4 — PWM5L output / bus RD4 |
| Broche 34 | QEI1A/RD5 — QEI1 channel A / bus RD5 |
| Broche 35 | QEI1B/RD6 — QEI1 channel B / bus RD6 |
| Broche 36 | QEI1INDX/RD7 — QEI1 index / bus RD7 |
| Broche 37 | RP16/RF0 — Remappable I/O RP16 / bus RF0 |
| Broche 38 | RP17/RF1 — Remappable I/O RP17 / bus RF1 |
| Broche 39 | RP18/RF2 — Remappable I/O RP18 / bus RF2 |
| Broche 40 | RP19/RF3 — Remappable I/O RP19 / bus RF3 |
| Broche 41 | RP20/RF4 — Remappable I/O RP20 / bus RF4 |
| Broche 42 | RP21/RF5 — Remappable I/O RP21 / bus RF5 |
| Broche 43 | RP22/RF6 — Remappable I/O RP22 / bus RF6 |
| Broche 44 | RP23/RF7 — Remappable I/O RP23 / bus RF7 |
| Broche 45 | VDD — Digital supply (+3.3 V) |
| Broche 46 | VSS — Digital ground |
| Broche 47 | RP24/RG0 — Remappable I/O RP24 / bus RG0 |
| Broche 48 | RP25/RG1 — Remappable I/O RP25 / bus RG1 |
| Broche 49 | RP26/RG2 — Remappable I/O RP26 / bus RG2 |
| Broche 50 | RP27/RG3 — Remappable I/O RP27 / bus RG3 |
| Broche 51 | TCKIA/RG6 — Timer clock input A / bus RG6 |
| Broche 52 | TCKIB/RG7 — Timer clock input B / bus RG7 |
| Broche 53 | TCKIC/RG8 — Timer clock input C / bus RG8 |
| Broche 54 | TCKID/RG9 — Timer clock input D / bus RG9 |
| Broche 55 | RA0 — PORTA bit 0 |
| Broche 56 | RA1 — PORTA bit 1 |
| Broche 57 | RA2 — PORTA bit 2 |
| Broche 58 | RA3 — PORTA bit 3 |
| Broche 59 | RA4 — PORTA bit 4 |
| Broche 60 | RA5 — PORTA bit 5 |
| Broche 61 | RA6 — PORTA bit 6 |
| Broche 62 | RA7 — PORTA bit 7 |
| Broche 63 | RB0 — PORTB bit 0 |
| Broche 64 | RB1 — PORTB bit 1 |
| Broche 65 | EP — Exposed pad - thermal dissipation, must be soldered to ground plane |
Applications typiques
DSPIC33FJ128MC706A-E/MR convient pour 6 applications: Brushless DC (BLDC) Motor Control, Three-Phase AC Induction Motor Drive (VFD), Switched Reluctance Motor (SRM) Controller, Uninterruptible Power Supply (UPS) Digital Control, Digital Switching Power Conversion (DC-DC), Automotive Sensorless Fan / Pump Controller.
Brushless DC (BLDC) Motor Control
The DSPIC33FJ128MC706A-E/MR is purpose-built for BLDC drives: its dedicated motor-control PWM provides 8 outputs with complementary mode and programmable dead-time, removing external timing logic. The 40 MIPS DSC core executes back-EMF zero-cross detection and 6-step commutation well within a 25 us control loop. The QEI module also enables sensored/hybrid schemes. With 128 KB Flash and 16 KB RAM, code space easily absorbs field-weakening and start-up routines; an exposed-pad 9x9 mm VQFN keeps the BOM small.
Recommandé
Three-Phase AC Induction Motor Drive (VFD)
Variable-frequency drives for AC induction motors demand sinusoidal PWM and field-oriented control. The DSPIC33FJ128MC706A-E/MR delivers 40 MIPS, which is sufficient for Clarke/Park transforms and a PI-based current-control loop in real time. The 6-channel 10-bit ADC samples phase currents at 1.1 Msps with simultaneous sampling, while the dedicated PWM keeps switching dead-time accurate to nanoseconds. Industrial -40C to +125C operation is supported by the "-E" suffix. The 16 KB RAM buffer is large enough for sliding-window FFT analysis on the same firmware.
Recommandé
Switched Reluctance Motor (SRM) Controller
SRM drives require high-speed, deterministic I/O handling for asymmetric half-bridge commutation. The DSPIC33FJ128MC706A-E/MR's 8 dedicated PWM outputs with complementary mode and dead-time match the typical 4-phase SRM half-bridge topology without external timing ICs. The integrated 8-channel DMA offloads ADC-to-PWM updates from the CPU, ensuring the rotor-position calculation runs every PWM period. Extended -40C to +125C operation and 9x9 mm VQFN suit automotive and industrial SR applications.
Recommandé
Uninterruptible Power Supply (UPS) Digital Control
In a UPS, the DSPIC33FJ128MC706A-E/MR acts as both the inverter controller and the PFC controller, executing voltage/current loops at 40 MIPS. Its single-cycle 16x16 MAC accelerates RMS and power-factor calculations; the 6-channel ADC synchronously samples line voltage, inductor current, and output voltage. The 128 KB Flash holds state-machine code for grid/battery transfer logic, while 16 KB RAM holds lookup tables for sine PWM. The exposed-pad VQFN provides low thermal resistance for continuous inverter operation.
Recommandé
Digital Switching Power Conversion (DC-DC)
For digital-control DC-DC converters, the DSPIC33FJ128MC706A-E/MR's high-resolution PWM and 1.1 Msps ADC form a tight feedback loop. The DSC engine executes type-II/type-III compensators at 200 kHz switching with margin for telemetry and monitoring. The 8-channel DMA streams ADC samples into RAM while the CPU runs the control law, sustaining deterministic bandwidth. Extended-temperature grade allows converter operation near power-stage heatsinks.
Recommandé
Automotive Sensorless Fan / Pump Controller
In 12 V automotive fan and coolant-pump applications, the DSPIC33FJ128MC706A-E/MR's 40 MIPS core runs sensorless back-EMF algorithms while the dedicated motor-control PWM drives a 3-phase bridge. The extended -40C to +125C temperature rating matches under-hood thermal stress. The small 9x9 mm VQFN footprint leaves PCB room for power-stage FETs, and the 16 KB RAM is sufficient for adaptive start-up tables. CAN or LIN can be implemented in software on the available UART/SPI peripherals.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour DSPIC33FJ128MC706A-E/MR — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | DSPIC33FJ128MC706A-I/MR | DSPIC33FJ128MC706AT-I/MR | DSPIC33FJ128MC706A-H/MR | DSPIC33FJ64MC706A-E/MR | DSPIC33FJ128MC506A-E/MR |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | VQFN-64 (9x9 mm) EP | VQFN-64 (9x9 mm) EP - same | VQFN-64 (9x9 mm) EP - same | VQFN-64 (9x9 mm) EP - same | VQFN-64 (9x9 mm) EP - same | VQFN-64 (9x9 mm) EP - same |
| CPU Speed | 40 MIPS / 40 MHz | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| Flash Memory | 128 KB | 128 KB | 128 KB | 128 KB | 64 KB (-50%) | 64 KB (-50%) |
| RAM | 16 KB | 16 KB | 16 KB | 16 KB | 8 KB (-50%) | 8 KB (-50%) |
| Operating Temperature | -40C to +125C (extended) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +125C (extended) | -40C to +125C (extended) | -40C to +125C (extended) |
| ADC | 10-bit, 1.1 Msps, 6 channels | 10-bit, 1.1 Msps, 6 channels | 10-bit, 1.1 Msps, 6 channels | 10-bit, 1.1 Msps, 6 channels | 10-bit, 1.1 Msps, 6 channels | 10-bit, 1.1 Msps, 6 channels |
| Motor Control PWM Outputs | 8 (with complementary mode + dead-time) | 8 | 8 | 8 | 8 | 8 |
Principaux différenciateurs
- Highest Flash density in the 706-series motor-control DSCs (vs DSPIC33FJ64MC706A-E/MR)
- Extended -40C to +125C operating range for harsh environments (vs DSPIC33FJ128MC706A-I/MR)
- Dedicated motor-control PWM with hardware dead-time and QEI (vs DSPIC33FJ128MC510A-I/PF)
- Smaller 9x9 mm VQFN footprint vs 100-pin TQFP alternatives (vs DSPIC33FJ128MC510A-E/PF)
Notes de conception
Estimated: For a 4-layer JEDEC JESD51 test board, theta-JA of the 9x9 mm VQFN-EP64 package is approximately 28 C/W. At continuous 40 MIPS operation with all peripherals active (typical IDD ~50 mA at 3.3 V), power dissipation is roughly 0.165 W, giving a self-heating rise of only ~5 C above ambient. The exposed pad MUST be soldered to a continuous ground copper pour with at least 25 thermal vias to the inner ground plane; failure to do so can push theta-JA above 60 C/W and compromise long-term reliability, especially in enclosed-VAC motor housings.
Place a 100 nF X7R decoupling capacitor within 3 mm of every VDD/VSS pair (pins 7, 15, 28, 45), plus a bulk 10 uF X5R capacitor on the analog AVDD rail (pin 7). Keep the analog ground AVSS (pin 8) star-connected to the digital ground VSS at a single point under the IC. Route crystal traces (OSC1/OSC2, pins 17-18) as short, symmetric, guard-banded traces with the load capacitors placed adjacent to the IC. PWM traces should be 0.2 mm wider than the signal-current requirement and never share return paths with sensitive analog (ADC) inputs.
Avoid three pitfalls common to first-time dsPIC33F designs: (1) forgetting to configure the oscillator in the FOSC configuration register, which can cause lock-up if the PLL is mistargeted; (2) leaving JTAG-enabled boundary-scan signals (PGEx) floating during normal operation - tie MCLR high through a 10 kohm pull-up and let PGEC/PGED float; (3) using the QEI module before clearing the POSCNT register after a homing sequence, which corrupts the next angle measurement. The MPLAB Code Configurator (MCC) plugin for MPLAB X eliminates most of these by generating correct init code.
Estimated: For a 3-phase inverter PCB, group the 6 PWM outputs (PWM1L/H through PWM3L/H on pins 1-6 and PWM4L/H on pins 30-31) into a tight fan-out cluster with matched trace lengths within 1 mm to keep propagation-delay skew below 5 ns. Place the ADC current-sense traces (AN0-AN5) orthogonally to the PWM traces to minimize capacitive coupling; if layout area is tight, route analog signals on the opposite side of the PCB with a continuous ground plane in between. Use 4-layer stack-up (sig/gnd/pwr/sig) rather than 2-layer for motor-control boards.
For QEI inputs at >1 MHz switching (e.g. 50 000 RPM with 1024 PPR), the QEA and QEB pins (RD5/RD6) should be guarded by a ground trace on each side and terminated at the IC with 100 ohms in parallel with 47 pF only if the encoder cable is longer than 200 mm. The QEI1INDX index signal (RD7) should be debounced in software if used with mechanical encoders. For SPI peripherals driving isolated gate drivers, place a small ferrite bead in series with the SCK line to dampen ringing from the isolator capacitance.
Informations de conformité
RoHS and lead-free per Microchip product page. Not AEC-Q100 qualified - automotive applications requiring formal qualification should contact Microchip for dsPIC33F automotive-grade variants. Conflict-minerals compliance follows Microchip corporate CMRT/CMCo declaration.
