DSPIC33FJ128MC706A-I/MR - 16-bit DSC 40MIPS 128KB Flash Motor Control | Microchip
MPN: DSPIC33FJ128MC706A-I/MR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9.42 | $9.42 |
| 10 | $8.75 | $87.50 |
| 100 | $7.98 | $798.00 |
| 500 | $7.21 | $3,605.00 |
| 1,000 | $6.54 | $6,540.00 |
DSPIC33FJ128MC706A-I/MR Overview
A Digital Signal Controller (DSC) is a hybrid architecture that merges a microcontroller's deterministic control peripherals with a DSP engine capable of executing single-cycle MAC operations, enabling tightly coupled real-time control and high-speed math in a single chip. Within the broader semiconductor taxonomy, the DSC sits between the microcontroller (MCU) and the digital signal processor (DSP), combining deterministic interrupt response, on-chip Flash, and signal-processing bandwidth; the dsPIC33F family specifically targets closed-loop control of motors, power converters, and sensors.
Key features include a 16-bit timer/counter architecture, multiple 16-bit and 32-bit capture inputs, comparators with 10-bit reference DACs, and a high-resolution PWM module suited to field-oriented control of three-phase motors. The device also integrates CAN 2.0B, I2C, SPI, and UART peripherals, plus a 10/12-bit ADC with up to 16 channels and 500 ksps throughput, allowing simultaneous sampling of motor phase currents and DC-bus voltage.
The DSP core executes single-cycle multiply-accumulate instructions and supports fractional arithmetic, giving it 40 MIPS sustained throughput for sinusoidal commutation algorithms, space-vector modulation, and PI control loops. With 128 KB Flash, full sensored or sensorless FOC algorithms for PMSM/BLDC motors fit on-chip, eliminating external memory. The 64-pin VQFN with exposed pad provides a low-thermal-resistance path suitable for sustained high-CPU-load industrial environments.
Typical applications include brushless DC (BLDC) motor drives, permanent-magnet synchronous motors (PMSM), single- and three-phase induction motor control, switched-reluctance drives, and automotive auxiliary motor systems. It is also well-suited for solar inverters, uninterruptible power supplies (UPS), and digital power conversion applications requiring deterministic PWM and DSP-grade math.
When designing with this part, allocate the Motor Control PWM channels to the three-phase inverter gate drivers and ensure the AVDD/AVSS analog supply pair is decoupled at the package pin to keep ADC readings clean. Use the on-chip DMA to offload ADC result transfers so the CPU is free to run the control loop at the PWM period rate. Watch maximum current on I/O pins if sinking encoder signals.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for DSPIC33FJ128MC706A-I/MR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ128MC706A-I/MR (same form factor and footprint) — differing in Package, Core Architecture, Operating Temperature, ADC, Timers.
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DSPIC33FJ128MC706AT-I/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$5.4 / Unit
View Datasheet →DSPIC33FJ128MC706A-H/MR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ128MC706A-E/MR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ128MC506A-I/MR
✅ Drop-In✓ In Stock
$4.42 / Unit
View Datasheet →DSPIC33FJ128MC506A-E/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$4.82 / Unit
View Datasheet →DSPIC33FJ128MC506A-H/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
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View Datasheet →DSPIC33FJ128MC706A-I/MR Maximum Ratings & Electrical Characteristics
| Core Architecture | dsPIC33F (16-bit DSC) |
| CPU Speed | 40 MIPS |
| Clock Speed | 40 MHz |
| Program Memory (Flash) | 128 KB |
| Data RAM | 16 KB |
| Supply Voltage | 3.0 V to 3.6 V |
| Package | VQFN-EP-64 (9x9 mm) |
| Mounting Type | Surface Mount |
| DMA Channels | 8 |
| Timers | 11 |
| Serial I/O Ports | 4 |
| ADC | 10/12-bit, up to 16 channels, 500 ksps |
| Motor Control PWM | Yes, integrated 3-phase capable |
| Operating Temperature | -40 C to +85 C (Industrial) |
| Pin Count | 64 |
| RoHS Status | Compliant |
DSPIC33FJ128MC706A-I/MR Pin Configuration
| Pin 1 | RP15/RG15 — Remappable I/O / GPIO |
| Pin 2 | VDD — Core logic supply 3.3 V |
| Pin 3 | VSS — Ground reference |
| Pin 4 | RP14/RG14 — Remappable I/O / GPIO |
| Pin 5 | OSC1 — Crystal oscillator input |
| Pin 6 | OSC2 — Crystal oscillator output |
| Pin 7 | RP13/RG13 — Remappable I/O / GPIO |
| Pin 8 | VDD — Core logic supply 3.3 V |
| Pin 9 | VSS — Ground reference |
| Pin 10 | RP12/RG12 — Remappable I/O / GPIO |
| Pin 11 | RP11/RG11 — Remappable I/O / GPIO |
| Pin 12 | RP10/RG10 — Remappable I/O / GPIO |
| Pin 13 | RP9/RG9 — Remappable I/O / GPIO |
| Pin 14 | MCLR — Master clear reset (active low) |
| Pin 15 | RP8/RG8 — Remappable I/O / GPIO |
| Pin 16 | AVDD — Analog supply 3.3 V |
| Pin 17 | AVSS — Analog ground |
| Pin 18 | AN0 — Analog input 0 |
| Pin 19 | AN1 — Analog input 1 |
| Pin 20 | AN2 — Analog input 2 |
| Pin 21 | AN3 — Analog input 3 |
| Pin 22 | AN4 — Analog input 4 |
| Pin 23 | AN5 — Analog input 5 |
| Pin 24 | AVSS — Analog ground |
| Pin 25 | AN7 — Analog input 7 |
| Pin 26 | AN8 — Analog input 8 |
| Pin 27 | AN9 — Analog input 9 |
| Pin 28 | AN10 — Analog input 10 |
| Pin 29 | AN11 — Analog input 11 |
| Pin 30 | AN12 — Analog input 12 |
| Pin 31 | AN13 — Analog input 13 |
| Pin 32 | AN14 — Analog input 14 |
| Pin 33 | AN15 — Analog input 15 |
| Pin 34 | AVDD — Analog supply 3.3 V |
| Pin 35 | VDD — Core logic supply 3.3 V |
| Pin 36 | VSS — Ground reference |
| Pin 37 | PWM1H — PWM 1 High output |
| Pin 38 | PWM1L — PWM 1 Low output |
| Pin 39 | PWM2H — PWM 2 High output |
| Pin 40 | PWM2L — PWM 2 Low output |
| Pin 41 | PWM3H — PWM 3 High output |
| Pin 42 | PWM3L — PWM 3 Low output |
| Pin 43 | RP0/RB0 — Remappable I/O / GPIO |
| Pin 44 | RP1/RB1 — Remappable I/O / GPIO |
| Pin 45 | RP2/RB2 — Remappable I/O / GPIO |
| Pin 46 | RP3/RB3 — Remappable I/O / GPIO |
| Pin 47 | RP4/RB4 — Remappable I/O / GPIO |
| Pin 48 | RP5/RB5 — Remappable I/O / GPIO |
| Pin 49 | VDD — Core logic supply 3.3 V |
| Pin 50 | VSS — Ground reference |
| Pin 51 | RP6/RB6 — Remappable I/O / GPIO |
| Pin 52 | RP7/RB7 — Remappable I/O / GPIO |
| Pin 53 | C1RX/RF0 — CAN 1 RX / remappable I/O |
| Pin 54 | C1TX/RF1 — CAN 1 TX / remappable I/O |
| Pin 55 | SDA1/RG3 — I2C 1 data |
| Pin 56 | SCL1/RG2 — I2C 1 clock |
| Pin 57 | U1RX/RF2 — UART 1 RX |
| Pin 58 | U1TX/RF3 — UART 1 TX |
| Pin 59 | SCK1/RF6 — SPI 1 clock |
| Pin 60 | SDI1/RF7 — SPI 1 data in |
| Pin 61 | SDO1/RF8 — SPI 1 data out |
| Pin 62 | SS1/RG9 — SPI 1 slave select |
| Pin 63 | TDI/RA0 — JTAG TDI |
| Pin 64 | EP — Exposed thermal pad (connect to VSS) |
Typical Applications
DSPIC33FJ128MC706A-I/MR is suitable for 7 applications: Brushless DC (BLDC) Motor Control, Permanent Magnet Synchronous Motor (PMSM) Field-Oriented Control, Three-Phase Induction Motor Drives, Switched Reluctance Motor (SRM) Control, Solar Microinverters and String Inverters, Uninterruptible Power Supplies (UPS) and Digital Power Conversion, Automotive Auxiliary Motor Systems.
Brushless DC (BLDC) Motor Control
DSPIC33FJ128MC706A-I/MR is well-suited for sensorless and sensored BLDC motor control through its integrated Motor Control PWM (3-phase capable) and 8 DMA channels that offload ADC transfers, freeing CPU cycles for the commutation loop. The 40 MIPS DSC engine executes trapezoidal and sinusoidal commutation algorithms in single-cycle MAC instructions, while the 10/12-bit ADC with 500 ksps throughput samples phase currents and DC-bus voltage simultaneously. The 128 KB Flash holds complete sensorless observer code plus commutation tables, and the 16 KB RAM buffers current loop state variables without off-chip memory. The VQFN-EP package provides low thermal resistance for sustained CPU load in enclosed motor drive housings.
Recommended
Permanent Magnet Synchronous Motor (PMSM) Field-Oriented Control
For PMSM field-oriented control (FOC), DSPIC33FJ128MC706A-I/MR delivers the required DSP bandwidth - 40 MIPS of fractional arithmetic at 40 MHz - to execute Park/Clarke transforms and space-vector modulation at 20 kHz PWM rates. The integrated Motor Control PWM module generates center-aligned complementary outputs with programmable dead time, while the 8 DMA channels stream ADC results into RAM without CPU intervention. The 128 KB Flash fits typical sensored FOC code including SVPWM lookup tables, and the 10/12-bit ADC captures shunt resistor currents for closed-loop torque control. Engineers typically pair this DSC with external gate drivers and current-sense amplifiers for a complete PMSM inverter.
Recommended
Three-Phase Induction Motor Drives
DSPIC33FJ128MC706A-I/MR drives single- and three-phase induction motors using V/F, vector, or direct torque control schemes. The 40 MIPS core runs sinusoidal PWM and scalar control algorithms with deterministic interrupt latency, while the 11 timers provide precise PWM generation and capture inputs for encoder feedback. The 128 KB Flash holds full V/F profiles and slip compensation tables for variable-torque applications such as fans, pumps, and compressors. Industrial-grade -40 C to +85 C operation and 64-pin package with exposed thermal pad support enclosed motor enclosures without active cooling.
Recommended
Switched Reluctance Motor (SRM) Control
Switched reluctance motors require precise torque-ripple-minimizing commutation logic that DSPIC33FJ128MC706A-I/MR handles through its Motor Control PWM with programmable dead bands and high-resolution duty control. The DSC's 40 MIPS sustained throughput computes position-based current profiling and demagnetization timing within microseconds, while the integrated comparators with 10-bit DAC references enable hardware overcurrent protection at microsecond response times. The 128 KB Flash accommodates lookup tables for rotor-position-to-phase-current mapping, and 16 KB RAM buffers fast-changing commutation variables without latency. The VQFN-EP package suits compact SRM inverter designs where board area is constrained.
Recommended
Solar Microinverters and String Inverters
DSPIC33FJ128MC706A-I/MR executes MPPT algorithms and grid-tie inverter control loops at the DSP throughput required by solar power conversion. The 40 MIPS DSC engine runs perturb-and-observe or incremental conductance MPPT at sub-second intervals, while the 16 KB RAM buffers ADC sample streams and 128 KB Flash holds grid-synchronization PLL code and protection firmware. The 10/12-bit ADC with 500 ksps captures panel voltage, current, and grid voltage with adequate resolution for maximum power point tracking. CAN, SPI, and UART peripherals interface to grid-monitoring modules and panel-level communications, making the device suitable for distributed solar inverter topologies.
Recommended
Uninterruptible Power Supplies (UPS) and Digital Power Conversion
DSPIC33FJ128MC706A-I/MR serves as the digital control core in UPS systems and digital power converters, executing voltage-mode and current-mode control loops with DSP-grade precision. The integrated Motor Control PWM and high-resolution timers generate the switching waveforms required for power-factor correction and DC-DC conversion stages, while the 8 DMA channels stream ADC conversions into the control loop without CPU overhead. The 40 MIPS core runs adaptive control algorithms at switching frequencies up to 500 kHz, and the 128 KB Flash holds full state-machine firmware for UPS transfer logic. Industrial temperature grade supports telecom and server-room UPS deployment.
Recommended
Automotive Auxiliary Motor Systems
DSPIC33FJ128MC706A-I/MR drives automotive auxiliary motors such as HVAC blowers, water pumps, oil pumps, and electronic throttle controls where deterministic PWM and DSP math are required. The integrated CAN 2.0B peripheral interfaces to vehicle networks, while the Motor Control PWM provides complementary 3-phase outputs with hardware dead-time insertion for safety-critical actuation. The 128 KB Flash stores application-specific FOC profiles and diagnostic routines, and the industrial -40 C to +85 C temperature grade handles under-hood thermal stress. For full AEC-Q100 automotive qualification, designers typically select a Q-graded variant or the higher-end MC710A family.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ128MC706A-I/MR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ128MC706AT-I/MR | DSPIC33FJ128MC706A-H/MR | DSPIC33FJ128MC706A-E/MR | DSPIC33FJ128MC506A-I/MR |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | VQFN-EP-64 (9x9 mm) | VQFN-EP-64 (9x9 mm) - same | VQFN-EP-64 (9x9 mm) - same | VQFN-EP-64 (9x9 mm) - same | VQFN-EP-64 (9x9 mm) - same |
| Flash Program Memory | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB |
| Data RAM | 16 KB | 16 KB | 16 KB | 16 KB | 16 KB |
| CPU Speed | 40 MIPS at 40 MHz | 40 MIPS at 40 MHz | 40 MIPS at 40 MHz | 40 MIPS at 40 MHz | 40 MIPS at 40 MHz |
| Operating Temperature | -40 C to +85 C (Industrial) | -40 C to +85 C | -40 C to +125 C (Extended H) | -40 C to +125 C (Extended E) | -40 C to +85 C |
| Motor Control PWM | Yes (3-phase capable) | Yes (3-phase) | Yes (3-phase) | Yes (3-phase) | Yes (reduced feature set) |
| Supply Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Approx 1-piece Price (USD) | $9.42 | Similar (~$9.42) | Higher (extended temp) | Higher (extended temp) | Lower (~$7.50) |
Key Differentiators
- Higher Flash + RAM in same pin-compatible VQFN package (vs DSPIC33FJ128MC506A-I/MR)
- Integrated 3-phase Motor Control PWM reduces external gate driver complexity (vs PIC24FJ256GA106 general-purpose MCU)
- Single-cycle DSP MAC engine at 40 MIPS (vs ARM Cortex-M0/M0+ 16-bit microcontrollers)
Design Notes
Estimated: at 40 MHz CPU + full motor control PWM + active ADC + CAN, the typical VDD current is around 35-50 mA depending on peripheral activity. The integrated voltage regulator requires a stable bulk capacitor of 10 uF (tantalum or ceramic) on VDD plus a 0.1 uF ceramic bypass placed within 5 mm of each VDD/VSS pin pair. For multi-rail designs, sequence the AVDD after VDD to keep ADC references stable at startup.
The VQFN-EP package exposes a thermal pad on the bottom that must be soldered to a copper pour on the PCB for heat dissipation. Theta-JA on a JEDEC 4-layer test board is approximately 28 C/W for this package; soldering the EP to a 1 square inch copper pad drops effective theta-JA to roughly 15-20 C/W. For sustained CPU load (continuous motor control loops), connect the EP directly to the ground plane with multiple thermal vias for optimal heat flow into the PCB.
Keep analog input traces (AN0-AN15) short and routed away from PWM switching signals to minimize coupled noise on ADC readings. Place the 0.1 uF and 10 uF decoupling capacitors on each AVDD/AVSS pair as close as possible to the package pins (within 3 mm). Use a guard ring tied to AVSS around analog traces if motor drive switching noise is severe. The exposed pad (pin 64) must be soldered for both thermal performance and electrical connection to VSS.
Do not exceed 3.6 V on VDD or 4.0 V on any I/O pin, as the dsPIC33F is not 5 V tolerant. Configure the JTAG pins (TDI/TDO/TCK/TMS) as GPIO in firmware if JTAG is unused, to free additional I/O. When using DMA with ADC, ensure DMA channel priority matches real-time requirements - DMA conflicts with the CPU during multi-channel high-speed ADC sampling can cause ADC overrun errors. Initialize unused comparators and PWM outputs to a defined low state to avoid spurious switching.
Route the crystal oscillator traces (OSC1/OSC2) symmetrically with short, parallel traces and guard them with a ground pour to avoid EMI pickup. For the Motor Control PWM outputs, route complementary pairs (PWM1H/PWM1L, etc.) together with matched trace lengths to keep propagation skew under 1 ns; this ensures clean dead-time insertion and prevents shoot-through in the inverter. CAN bus traces should be routed as a differential pair with 120 ohm characteristic impedance and terminated at both ends.
Compliance Information
RoHS compliant per Microchip product page. Not AEC-Q100 qualified - for automotive designs, review Microchip automotive-grade catalog.
