EPF10K10AQC208-3N - 10K-Gate FLEX 10KA FPGA, 208-PQFP | Intel
Référence : EPF10K10AQC208-3N ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $75 | $75,00 |
| 10 | $68.5 | $685,00 |
| 100 | $60.25 | $6 025,00 |
| 250 | $54.75 | $13 687,50 |
| 500 | $49.9 | $24 950,00 |
EPF10K10AQC208-3N Présentation
A Field Programmable Gate Array (FPGA) is a semiconductor IC containing an array of configurable logic blocks (CLBs), embedded memory, and programmable interconnect fabric. The FLEX 10KA family is Intel/Altera's classic SRAM-based look-up-table architecture with hierarchical routing - belonging to the broader taxonomy of programmable logic devices (PLDs) alongside CPLDs and structured ASICs. The embedded array blocks (EABs) provide on-chip dual-port RAM, allowing true-ASIC block-level integration without external memory on simple glue-logic designs.
Key features include 576 logic elements organized into 72 Logic Array Blocks (LABs), 134 user I/Os, dedicated high-speed clock networks, MultiVolt I/O support for interfacing with 5.0 V, 3.3 V, and 2.5 V systems, and JTAG-compliant boundary-scan test support. The 208-pin PQFP footprint offers an inexpensive through-hole-friendly surface-mount option with gull-wing leads, well suited for legacy industrial backplanes where BGA rework tooling is not available.
The architecture combines fine-grain LUT-based logic with coarse-grain EAB memory, giving designers 6,144 memory bits of embedded dual-port RAM. Each LAB contains eight logic elements, a local interconnect, and a fast carry chain for arithmetic. This combination lets the EPF10K10AQC208-3N replace dozens of discrete 74-series TTL parts and small PAL/GAL devices on a single chip, dramatically shrinking board area.
Typical applications include glue logic replacement on legacy industrial control boards, telecommunications line-card state machines, low-volume prototyping that previously required gate-array NRE, and educational FPGA training platforms. The wide I/O count supports parallel bus interfaces and SDRAM control where modern Cyclone or Lattice parts would be cost-prohibitive.
When designing with this device, plan for 3.3 V core supply with separate VCCIO banks for mixed-voltage I/O. Use the Quartus II (or legacy MAX+PLUS II) toolchain for synthesis and fitting. Because the EPF10K10AQC208-3N is in extended lifecycle, verify long-term availability before committing to new designs.
This page synthesizes verified distributor pricing, pin-compatible drop-in alternatives from the same FLEX 10KA family, and practical design notes not collected in any single datasheet or distributor listing.
Alternatives de remplacement direct pour EPF10K10AQC208-3N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPF10K10AQC208-3N (même facteur de forme et même empreinte) — différant par Package, Configuration Method, Family, Process Technology, Operating Temperature.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPF10K10AQC208-2
✅ Remplacement direct✓ En stock
$22 / unité
Voir la fiche technique →EPF10K10AQC208-3
✅ Remplacement direct✓ En stock
$31.4 / unité
Voir la fiche technique →EPF10K10AQC208-1
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EPF10K10ATC100-3N
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$9.95 / unité
Voir la fiche technique →EPF10K10AQC208-3N
✅ Remplacement direct✓ En stock
$49.9 / unité
Voir la fiche technique →EPF10K10AQC208-3N Valeurs maximales et caractéristiques électriques
| Series | FLEX 10KA |
| Family | FLEX 10KA (SRAM-based FPGA) |
| Logic Elements / Cells | 576 |
| Usable Gates | 10,000 |
| Logic Array Blocks (LABs) | 72 |
| User I/Os | 134 |
| Embedded Memory Bits | 6,144 |
| Number of Embedded RAM Blocks (EABs) | 3 |
| Core Voltage | 3.3 V |
| Plage de température de fonctionnement | 0 °C to +70 °C (Commercial) |
| Speed Grade | -3 |
| Maximum Internal Frequency | 125 MHz |
| Process Technology | 0.3 µm CMOS |
| Package Type | 208-BFQFP (PQFP) |
| Style de montage | Surface Mount |
| Lead Form | Gull-wing |
| Voltage - Supply | 3.3 V |
Configuration des broches de EPF10K10AQC208-3N
| Broche 1 | I/O — User I/O - bank 1 |
| Broche 2 | I/O — User I/O - bank 1 |
| Broche 3 | I/O — User I/O - bank 1 |
| Broche 4 | I/O — User I/O - bank 1 |
| Broche 5 | VCCIO1 — I/O bank 1 supply voltage |
| Broche 6 | I/O — User I/O - bank 1 |
| Broche 7 | I/O — User I/O - bank 1 |
| Broche 8 | I/O — User I/O - bank 1 |
| Broche 9 | GND — Ground |
| Broche 10 | I/O — User I/O - bank 1 |
| Broche 11 | I/O — User I/O - bank 1 |
| Broche 12 | I/O — User I/O - bank 1 |
| Broche 13 | I/O — User I/O - bank 1 |
| Broche 14 | I/O — User I/O - bank 1 |
| Broche 15 | I/O — User I/O - bank 1 |
| Broche 16 | I/O — User I/O - bank 1 |
| Broche 17 | I/O — User I/O - bank 1 |
| Broche 18 | I/O — User I/O - bank 1 |
| Broche 19 | I/O — User I/O - bank 1 |
| Broche 20 | GND — Ground |
| Broche 21 | I/O — User I/O - bank 1 |
| Broche 22 | I/O — User I/O - bank 1 |
| Broche 23 | I/O — User I/O - bank 1 |
| Broche 24 | I/O — User I/O - bank 1 |
| Broche 25 | I/O — User I/O - bank 1 |
| Broche 26 | I/O — User I/O - bank 1 |
| Broche 27 | I/O — User I/O - bank 1 |
| Broche 28 | VCCINT — Core supply voltage 3.3 V |
| Broche 29 | I/O — User I/O - bank 2 |
| Broche 30 | I/O — User I/O - bank 2 |
| Broche 31 | I/O — User I/O - bank 2 |
| Broche 32 | I/O — User I/O - bank 2 |
| Broche 33 | I/O — User I/O - bank 2 |
| Broche 34 | I/O — User I/O - bank 2 |
| Broche 35 | I/O — User I/O - bank 2 |
| Broche 36 | I/O — User I/O - bank 2 |
| Broche 37 | I/O — User I/O - bank 2 |
| Broche 38 | GND — Ground |
| Broche 39 | I/O — User I/O - bank 2 |
| Broche 40 | I/O — User I/O - bank 2 |
| Broche 41 | I/O — User I/O - bank 2 |
| Broche 42 | I/O — User I/O - bank 2 |
| Broche 43 | I/O — User I/O - bank 2 |
| Broche 44 | I/O — User I/O - bank 2 |
| Broche 45 | I/O — User I/O - bank 2 |
| Broche 46 | I/O — User I/O - bank 2 |
| Broche 47 | I/O — User I/O - bank 2 |
| Broche 48 | I/O — User I/O - bank 2 |
| Broche 49 | I/O — User I/O - bank 2 |
| Broche 50 | I/O — User I/O - bank 2 |
| Broche 51 | I/O — User I/O - bank 2 |
| Broche 52 | GND — Ground |
| Broche 53 | I/O — User I/O - bank 2 |
| Broche 54 | I/O — User I/O - bank 2 |
| Broche 55 | I/O — User I/O - bank 2 |
| Broche 56 | I/O — User I/O - bank 2 |
| Broche 57 | I/O — User I/O - bank 2 |
| Broche 58 | I/O — User I/O - bank 2 |
| Broche 59 | I/O — User I/O - bank 2 |
| Broche 60 | I/O — User I/O - bank 2 |
| Broche 61 | I/O — User I/O - bank 2 |
| Broche 62 | VCCIO2 — I/O bank 2 supply voltage |
| Broche 63 | I/O — User I/O - bank 2 |
| Broche 64 | I/O — User I/O - bank 2 |
| Broche 65 | I/O — User I/O - bank 2 |
| Broche 66 | I/O — User I/O - bank 2 |
| Broche 67 | I/O — User I/O - bank 2 |
| Broche 68 | I/O — User I/O - bank 2 |
| Broche 69 | I/O — User I/O - bank 2 |
| Broche 70 | I/O — User I/O - bank 2 |
| Broche 71 | I/O — User I/O - bank 2 |
| Broche 72 | GND — Ground |
| Broche 73 | I/O — User I/O - bank 3 |
| Broche 74 | I/O — User I/O - bank 3 |
| Broche 75 | I/O — User I/O - bank 3 |
| Broche 76 | I/O — User I/O - bank 3 |
| Broche 77 | I/O — User I/O - bank 3 |
| Broche 78 | I/O — User I/O - bank 3 |
| Broche 79 | I/O — User I/O - bank 3 |
| Broche 80 | VCCINT — Core supply voltage 3.3 V |
| Broche 81 | I/O — User I/O - bank 3 |
| Broche 82 | I/O — User I/O - bank 3 |
| Broche 83 | I/O — User I/O - bank 3 |
| Broche 84 | I/O — User I/O - bank 3 |
| Broche 85 | I/O — User I/O - bank 3 |
| Broche 86 | I/O — User I/O - bank 3 |
| Broche 87 | I/O — User I/O - bank 3 |
| Broche 88 | I/O — User I/O - bank 3 |
| Broche 89 | GND — Ground |
| Broche 90 | I/O — User I/O - bank 3 |
| Broche 91 | I/O — User I/O - bank 3 |
| Broche 92 | I/O — User I/O - bank 3 |
| Broche 93 | I/O — User I/O - bank 3 |
| Broche 94 | I/O — User I/O - bank 3 |
| Broche 95 | I/O — User I/O - bank 3 |
| Broche 96 | I/O — User I/O - bank 3 |
| Broche 97 | I/O — User I/O - bank 3 |
| Broche 98 | I/O — User I/O - bank 3 |
| Broche 99 | I/O — User I/O - bank 3 |
| Broche 100 | VCCIO3 — I/O bank 3 supply voltage |
| Broche 101 | I/O — User I/O - bank 3 |
| Broche 102 | I/O — User I/O - bank 3 |
| Broche 103 | I/O — User I/O - bank 3 |
| Broche 104 | I/O — User I/O - bank 3 |
| Broche 105 | I/O — User I/O - bank 3 |
| Broche 106 | I/O — User I/O - bank 3 |
| Broche 107 | I/O — User I/O - bank 3 |
| Broche 108 | I/O — User I/O - bank 3 |
| Broche 109 | GND — Ground |
| Broche 110 | I/O — User I/O - bank 4 |
| Broche 111 | I/O — User I/O - bank 4 |
| Broche 112 | I/O — User I/O - bank 4 |
| Broche 113 | I/O — User I/O - bank 4 |
| Broche 114 | I/O — User I/O - bank 4 |
| Broche 115 | I/O — User I/O - bank 4 |
| Broche 116 | I/O — User I/O - bank 4 |
| Broche 117 | VCCINT — Core supply voltage 3.3 V |
| Broche 118 | I/O — User I/O - bank 4 |
| Broche 119 | I/O — User I/O - bank 4 |
| Broche 120 | I/O — User I/O - bank 4 |
| Broche 121 | I/O — User I/O - bank 4 |
| Broche 122 | I/O — User I/O - bank 4 |
| Broche 123 | I/O — User I/O - bank 4 |
| Broche 124 | I/O — User I/O - bank 4 |
| Broche 125 | I/O — User I/O - bank 4 |
| Broche 126 | GND — Ground |
| Broche 127 | I/O — User I/O - bank 4 |
| Broche 128 | I/O — User I/O - bank 4 |
| Broche 129 | I/O — User I/O - bank 4 |
| Broche 130 | I/O — User I/O - bank 4 |
| Broche 131 | I/O — User I/O - bank 4 |
| Broche 132 | I/O — User I/O - bank 4 |
| Broche 133 | I/O — User I/O - bank 4 |
| Broche 134 | VCCIO4 — I/O bank 4 supply voltage |
| Broche 135 | I/O — User I/O - bank 4 |
| Broche 136 | I/O — User I/O - bank 4 |
| Broche 137 | I/O — User I/O - bank 4 |
| Broche 138 | I/O — User I/O - bank 4 |
| Broche 139 | I/O — User I/O - bank 4 |
| Broche 140 | I/O — User I/O - bank 4 |
| Broche 141 | I/O — User I/O - bank 4 |
| Broche 142 | I/O — User I/O - bank 4 |
| Broche 143 | GND — Ground |
| Broche 144 | I/O — User I/O - bank 4 |
| Broche 145 | I/O — User I/O - bank 4 |
| Broche 146 | I/O — User I/O - bank 4 |
| Broche 147 | I/O — User I/O - bank 4 |
| Broche 148 | I/O — User I/O - bank 4 |
| Broche 149 | I/O — User I/O - bank 4 |
| Broche 150 | I/O — User I/O - bank 4 |
| Broche 151 | I/O — User I/O - bank 4 |
| Broche 152 | VCCINT — Core supply voltage 3.3 V |
| Broche 153 | I/O — User I/O - bank 5 |
| Broche 154 | I/O — User I/O - bank 5 |
| Broche 155 | I/O — User I/O - bank 5 |
| Broche 156 | I/O — User I/O - bank 5 |
| Broche 157 | I/O — User I/O - bank 5 |
| Broche 158 | I/O — User I/O - bank 5 |
| Broche 159 | I/O — User I/O - bank 5 |
| Broche 160 | GND — Ground |
| Broche 161 | I/O — User I/O - bank 5 |
| Broche 162 | I/O — User I/O - bank 5 |
| Broche 163 | I/O — User I/O - bank 5 |
| Broche 164 | I/O — User I/O - bank 5 |
| Broche 165 | I/O — User I/O - bank 5 |
| Broche 166 | I/O — User I/O - bank 5 |
| Broche 167 | I/O — User I/O - bank 5 |
| Broche 168 | VCCIO5 — I/O bank 5 supply voltage |
| Broche 169 | I/O — User I/O - bank 5 |
| Broche 170 | I/O — User I/O - bank 5 |
| Broche 171 | I/O — User I/O - bank 5 |
| Broche 172 | I/O — User I/O - bank 5 |
| Broche 173 | I/O — User I/O - bank 5 |
| Broche 174 | I/O — User I/O - bank 5 |
| Broche 175 | I/O — User I/O - bank 5 |
| Broche 176 | I/O — User I/O - bank 5 |
| Broche 177 | GND — Ground |
| Broche 178 | TDI — JTAG Test Data In |
| Broche 179 | TRST — JTAG Test Reset |
| Broche 180 | TMS — JTAG Test Mode Select |
| Broche 181 | TCK — JTAG Test Clock |
| Broche 182 | TDO — JTAG Test Data Out |
| Broche 183 | nCONFIG — Configuration control (active low) |
| Broche 184 | nSTATUS — Configuration status (active low) |
| Broche 185 | CONF_DONE — Configuration done indicator |
| Broche 186 | DCLK — Configuration clock |
| Broche 187 | DATA0 — Configuration data input |
| Broche 188 | nCE — Chip enable (active low) |
| Broche 189 | nCEO — Chip enable out (active low) |
| Broche 190 | CLK0 — Dedicated clock input 0 |
| Broche 191 | CLK1 — Dedicated clock input 1 |
| Broche 192 | DEV_CLRn — Device clear (active low) |
| Broche 193 | DEV_OE — Device output enable |
| Broche 194 | VCCINT — Core supply voltage 3.3 V |
| Broche 195 | GND — Ground |
| Broche 196 | I/O — User I/O - bank 6 |
| Broche 197 | I/O — User I/O - bank 6 |
| Broche 198 | I/O — User I/O - bank 6 |
| Broche 199 | I/O — User I/O - bank 6 |
| Broche 200 | I/O — User I/O - bank 6 |
| Broche 201 | I/O — User I/O - bank 6 |
| Broche 202 | I/O — User I/O - bank 6 |
| Broche 203 | I/O — User I/O - bank 6 |
| Broche 204 | I/O — User I/O - bank 6 |
| Broche 205 | GND — Ground |
| Broche 206 | VCCIO6 — I/O bank 6 supply voltage |
| Broche 207 | I/O — User I/O - bank 6 |
| Broche 208 | I/O — User I/O - bank 6 |
Applications typiques
EPF10K10AQC208-3N convient pour 6 applications: Legacy Industrial Glue Logic Replacement, Telecommunications Line-Card State Machine, Low-Volume Prototyping Bridge to ASIC, FPGA Education and Training Platforms, Medical Device Interface Controllers, Mil/Aero Avionics Retrofit.
Legacy Industrial Glue Logic Replacement
The EPF10K10AQC208-3N excels at replacing dozens of discrete 74-series TTL logic gates, PAL/GAL devices, and small gate arrays on legacy industrial control boards. Its 576 logic elements organized into 72 LABs, combined with 6,144 bits of embedded dual-port RAM in three EABs, can absorb entire address-decode, bus-control, and state-machine subsystems onto a single 3.3 V chip. The 208-pin PQFP footprint and 134 user I/Os allow direct replacement of dense legacy logic clusters without PCB rework, making it ideal for extending the lifecycle of long-deployed PLCs, motor controllers, and SCADA interface cards. Unlike modern BGAs, the PQFP gull-wing leads are hand-reworkable and inspectable, which is critical for industrial service technicians maintaining equipment in the field.
Recommandé
Telecommunications Line-Card State Machine
Telecommunications line cards and DSLAMs deployed in the early 2000s frequently used FLEX 10KA family FPGAs as glue logic between PHYs, framers, and network processors. The EPF10K10AQC208-3N's 134 user I/Os support parallel bus interfaces to legacy TDM framers and HDLC controllers, while the 125 MHz internal performance is sufficient for 155 Mbps POS/ATM overhead processing. Its MultiVolt I/O allows direct interfacing with 5.0 V, 3.3 V, and 2.5 V devices on the same line card, eliminating level translators. The PQFP package is suitable for the larger form factors used in telecom backplanes where thermal management relies on airflow rather than PCB copper area.
Recommandé
Low-Volume Prototyping Bridge to ASIC
The EPF10K10AQC208-3N is well suited as a low-volume pre-ASIC prototype for designs that will eventually migrate to a gate-array or structured ASIC. Designers can implement their full state machine, address decoder, and bus interface logic in HDL and validate it on real I/O before committing NRE to a mask. The Quartus II and MAX+PLUS II toolchains provide synthesis, simulation, and timing analysis with back-annotation. The 208-pin PQFP offers easy socketing for rapid board iteration. Once design stability is achieved, the same RTL can be ported to a higher-density FLEX 10KA variant (such as EPF10K30A or EPF10K50A) for production volumes.
Recommandé
FPGA Education and Training Platforms
The EPF10K10AQC208-3N remains a popular FPGA for university digital-design laboratories and embedded-systems training courses. Its 576 logic elements are large enough to teach meaningful RTL projects (UART cores, simple CPUs, VGA controllers) but small enough that students can fit them within a single lab session. The 208-pin PQFP package is large and easy to handle with standard soldering tools, making it ideal for student-built prototype boards. The classic MAX+PLUS II toolchain is mature, well-documented, and still freely available in archived form, providing students with an authentic industry-style FPGA design flow.
Recommandé
Medical Device Interface Controllers
In long-lifecycle medical devices (patient monitors, infusion pumps, diagnostic analyzers), the EPF10K10AQC208-3N serves as a deterministic interface controller between sensor front-ends and main processors. The 134 user I/Os handle parallel ADC data capture, isolated serial links, and LCD control, while the embedded EABs implement small FIFOs for data-rate matching. The 3.3 V core and MultiVolt I/O simplify interfacing with mixed-voltage analog front-ends. Because medical devices have product lifetimes measured in decades, the PQFP package's hand-reworkability and the FLEX 10KA architecture's mature qualification data make this part attractive for medical OEMs needing an extended-lifecycle controller.
Recommandé
Mil/Aero Avionics Retrofit
Military and aerospace platforms with decades-long service lives still rely on the FLEX 10KA family for retrofit and repair of legacy avionics, radar interfaces, and flight-control subsystems. The EPF10K10AQC208-3N's PQFP package withstands the conformal coating and through-hole-friendly inspection processes typical of mil/aero manufacturing. Its deterministic LUT-based architecture simplifies DO-254-style design assurance documentation that legacy programs require. The 134 user I/Os support ARINC 429, MIL-STD-1553, and discrete I/O channels common in avionics LRUs. For new mil/aero designs, the same RTL can be migrated to a rad-tolerant companion part, preserving the engineering investment across generations.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPF10K10AQC208-3N — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPF10K10AQC208-2 | EPF10K10AQC208-3 | EPF10K10AQC208-1 | EPF10K10ATC100-3N |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 208-PQFP (BFQFP) | 208-PQFP (BFQFP) - same | 208-PQFP (BFQFP) - same | 208-PQFP (BFQFP) - same | 100-PQFP - different |
| Logic Elements | 576 | 576 - same | 576 - same | 576 - same | 576 - same |
| Usable Gates | 10,000 | 10,000 - same | 10,000 - same | 10,000 - same | 10,000 - same |
| User I/Os | 134 | 134 - same | 134 - same | 134 - same | 66 (-51%) |
| Speed Grade | -3 | -2 (faster) | -3 (same) | -1 (fastest) | -3 (same) |
| Core Voltage | 3.3 V | 3.3 V - same | 3.3 V - same | 3.3 V - same | 3.3 V - same |
| Operating Temperature | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
Principaux différenciateurs
- Identical FLEX 10KA die as -2 and -1 speed grades - true drop-in with speed-grade trade-off (vs EPF10K10AQC208-2)
- Lead-free (N) terminal finish - RoHS compliant for new builds (vs EPF10K10AQC208-3)
- Full 134 I/O count in 208-PQFP - higher density than 100-pin variant (vs EPF10K10ATC100-3N)
Notes de conception
The EPF10K10AQC208-3N requires a stable 3.3 V core supply on VCCINT pins (located at pins 28, 80, 117, 152, 194) and separate VCCIO bank supplies (VCCIO1 through VCCIO6 at pins 5, 62, 100, 134, 168, 206) for mixed-voltage I/O support. Decouple each VCCINT pin with a 0.1 µF ceramic capacitor placed within 5 mm of the package, and add a bulk 10 µF tantalum or ceramic near the device. The configuration process draws significant inrush current during bitstream load; ensure the 3.3 V regulator can source at least 500 mA peak during configuration. MultiVolt I/O banks allow 5.0 V, 3.3 V, or 2.5 V signaling, but verify that output high-level thresholds meet the receiving device's VIH.
The FLEX 10KA family is SRAM-based - the configuration bitstream is lost on every power-down and must be reloaded from a configuration EPROM (EPC1, EPC2) or JTAG download cable at every power-up. Do not omit the configuration memory in production designs. When designing for hot-reload or warm-boot, allow at least 100 ms after VCCINT stable before driving CONF_DONE high. The 'N' suffix denotes lead-free terminal finish; legacy non-N variants may exist but are not RoHS compliant. Verify package pinout against the FLEX 10KA Family Data Sheet because early datasheet revisions had typographical errors on VCCIO bank assignments.
The 208-pin PQFP has 0.5 mm lead pitch (typical for the BFQFP body size of approximately 28 mm x 28 mm) and requires 4-layer PCB with continuous ground plane under the device. Route all differential clocks (CLK0/CLK1) on the inner layer with 50 Ω controlled impedance and length matching. Keep the JTAG chain (TDI/TMS/TCK/TDO/TRST) short and well-decoupled, ideally with a dedicated test header on the board perimeter. Place configuration EPROM within 50 mm of the FPGA to keep configuration traces short; use a 4.7 kΩ pull-up on nCONFIG and nSTATUS to VCCINT.
Informations de conformité
RoHS compliant per the 'N' suffix designation in the part number. REACH compliance confirmed by Intel PSG documentation. AEC-Q100 not applicable for FPGAs. Lead-free (Pb-free) matte-tin finish on the PQFP gull-wing leads. Halogen-free status not verified in available data.