EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
Référence : EPM3128ATC100-10N ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $10.13 | $10,13 |
| 10 | $9.12 | $91,20 |
| 100 | $7.85 | $785,00 |
| 500 | $6.9 | $3 450,00 |
| 1 000 | $5.95 | $5 950,00 |
| 3 000 | $5.2 | $15 600,00 |
EPM3128ATC100-10N Présentation
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style macrocell arrays with a central programmable interconnect matrix. CPLDs sit in the hierarchy between simple SPLDs (PALs/GALs) and larger FPGAs, offering deterministic, single-clock-cycle propagation delays and instant-on non-volatile configuration. The MAX 3000A family uses CMOS EEPROM configuration memory, IEEE Std. 1532-compliant in-system programmability (ISP), and belongs to the broader power-management and logic-IC semiconductor category.
Key features include 128 macrocells (2500 usable gates), 80 user I/O pins, an internal fMAX of 98 MHz (per the FPGAkey datasheet summary), 3.3 V VCCINT operation, and selectable 3.3 V or 2.5 V VCCIO banks for mixed-voltage I/O. The device is pin-compatible with other MAX 3000A 100-pin TQFP variants and supports JTAG-based boundary-scan testing alongside ISP. The non-volatile EEPROM cells eliminate the need for an external boot PROM and the part powers up instantly in a user-defined state.
Architecturally, the EPM3128ATC100-10N organizes its 128 macrocells into 8 Logic Array Blocks (LABs) of 16 macrocells each, connected through a Programmable Interconnect Array (PIA). Each macrocell contains a programmable AND/OR array feeding a configurable flip-flop with product-term clock, clear, and preset controls, supporting combinatorial, registered, and buried logic without consuming I/O.
Typical applications include I/O expansion and bus bridging on legacy glue-logic boards, address decoding and interrupt steering on industrial controllers, state-machine replacement in white-goods motor control, and pin-compatible MAX 3000A migration paths. Designers in factory automation, telecom line cards, and embedded computing rely on this part for deterministic timing and field-reprogrammability.
Designers should pay attention to VCCIO bank configuration: 3.3 V allows direct interface to 3.3 V logic, while 2.5 V setting enables 2.5 V system compatibility. The I/O pins share a common bus-friendly structure but each LAB region can source/sink up to 25 mA per pin with proper thermal management across the 100-pin TQFP (θJA around 35-40 °C/W depending on PCB copper). Avoid daisy-chaining JTAG; use a star topology for ISP chains longer than 4 devices.
This page synthesizes distributor pricing, IEEE Std. 1532 ISP-compatible drop-in alternatives, and practical design notes not consolidated in the manufacturer datasheet alone. Real-time stock and parametric comparison are derived from DigiKey, Mouser, Octopart, and LCSC as of 2026-09-12.
Alternatives de remplacement direct pour EPM3128ATC100-10N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPM3128ATC100-10N (même facteur de forme et même empreinte) — différant par Package, Operating Temperature, Configuration Memory, In-System Programmability, User I/Os.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPM3128ATC100-10
✅ Remplacement direct✓ En stock
$8.1 / unité
Voir la fiche technique →EPM3128ATC100-7N
✅ Remplacement direct✓ En stock
$3.52 / unité
Voir la fiche technique →EPM3128ATC100-10N
✅ Remplacement direct✓ En stock
$5.2 / unité
Voir la fiche technique →EPM3128AFC256-7N
✅ Remplacement direct✓ En stock
$19.85 / unité
Voir la fiche technique →EPM3128ATC100-10N Valeurs maximales et caractéristiques électriques
| Family | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2500 |
| Number of I/O | 80 |
| Logic Elements / Blocks | 8 LABs (16 macrocells each) |
| Propagation Delay (tPD) | 10 ns |
| Maximum Internal Frequency (fMAX) | 98 MHz |
| Supply Voltage VCCINT | 3.3 V |
| I/O Bank Voltage VCCIO | 3.3 V or 2.5 V (selectable) |
| Configuration Memory | CMOS EEPROM (non-volatile, instant-on) |
| In-System Programming | IEEE Std. 1532-compliant ISP via JTAG |
| Boîtier | 100-pin TQFP (14 x 14 x 1.0 mm) |
| Température de fonctionnement | 0 °C to +70 °C (commercial) |
| Type de montage | Surface Mount |
| Statut RoHS | Compliant |
| Lead-Free | Yes |
| Niveau MSL | 3 (per JEDEC J-STD-020) |
Configuration des broches de EPM3128ATC100-10N
| Broche 1 | GND — Ground reference |
| Broche 2 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 3 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 4 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 5 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 6 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 7 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 8 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 9 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 10 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 11 | VCCINT — Core 3.3 V supply |
| Broche 12 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 13 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 14 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 15 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 16 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 17 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 18 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 19 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 20 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 21 | GND — Ground reference |
| Broche 22 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 23 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 24 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 25 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 26 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 27 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 28 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 29 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 30 | I/O — Bidirectional user I/O pin (bank 2) |
| Broche 31 | GND — Ground reference |
| Broche 32 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 33 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 34 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 35 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 36 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 37 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 38 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 39 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 40 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 41 | VCCINT — Core 3.3 V supply |
| Broche 42 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 43 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 44 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 45 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 46 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 47 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 48 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 49 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 50 | I/O — Bidirectional user I/O pin (bank 3) |
| Broche 51 | GND — Ground reference |
| Broche 52 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 53 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 54 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 55 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 56 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 57 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 58 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 59 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 60 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 61 | GND — Ground reference |
| Broche 62 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 63 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 64 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 65 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 66 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 67 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 68 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 69 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 70 | I/O — Bidirectional user I/O pin (bank 4) |
| Broche 71 | GND — Ground reference |
| Broche 72 | TDI — JTAG Test Data In (ISP programming) |
| Broche 73 | TMS — JTAG Test Mode Select (ISP programming) |
| Broche 74 | TCK — JTAG Test Clock (ISP programming) |
| Broche 75 | NC — Not connected (per datasheet) |
| Broche 76 | VCCIO — I/O bank supply (3.3 V or 2.5 V) |
| Broche 77 | GCLK — Global clock input (dedicated) |
| Broche 78 | OE — Global Output Enable (dedicated input) |
| Broche 79 | NC — Not connected (per datasheet) |
| Broche 80 | VCCIO — I/O bank supply (3.3 V or 2.5 V) |
| Broche 81 | GND — Ground reference |
| Broche 82 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 83 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 84 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 85 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 86 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 87 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 88 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 89 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 90 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 91 | GND — Ground reference |
| Broche 92 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 93 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 94 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 95 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 96 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 97 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 98 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 99 | I/O — Bidirectional user I/O pin (bank 1) |
| Broche 100 | TDO — JTAG Test Data Out (ISP programming) |
Applications typiques
EPM3128ATC100-10N convient pour 6 applications: Address Decoding & Bus Bridging on Legacy Glue Logic, Industrial Control State Machine Replacement, Telecom Line-Card I/O Expansion, Embedded Computing Glue Logic in Single-Board Computers, White-Goods Motor Control and Appliance Logic, Test & Measurement Equipment Front-End Logic.
Address Decoding & Bus Bridging on Legacy Glue Logic
The EPM3128ATC100-10N fits address decoding and bus-bridging roles because its 10 ns pin-to-pin propagation delay is deterministic and its 128 macrocells provide abundant product-term capacity for complex Chip-Select and interrupt-steering logic. Placed between a 3.3 V microcontroller and asynchronous peripheral buses, the device replaces 4-8 discrete PAL/GAL chips with a single in-system-reprogrammable CPLD, cutting PCB area by up to 60%. The IEEE Std. 1532 ISP interface lets field technicians update decode maps without desoldering the part, a key advantage over legacy bipolar PALs.
Recommandé
Industrial Control State Machine Replacement
The EPM3128ATC100-10N is well-suited to replace discrete 74LS/74HC state machines in industrial controllers because its 98 MHz fMAX and 8 LABs support complex Moore/Mealy sequencers without microsequencer overhead. Its 80 user I/O pins map directly to typical PLC backplanes (32 inputs + 32 outputs + 16 control lines), and the non-volatile EEPROM means the controller boots into its last programmed state without an external boot PROM. The 3.3 V/2.5 V VCCIO flexibility lets the same board drive both 5 V-tolerant buffers (through level shifters) and native 2.5 V ASICs in mixed-voltage subsystems.
Recommandé
Telecom Line-Card I/O Expansion
Telecom line cards use the EPM3128ATC100-10N as a low-cost I/O expander because its 80 I/O pins comfortably aggregate 16-32 E1/T1 channels, and the 10 ns tPD preserves timing margins for HDLC framing at 2.048 Mbps. The CPLD's deterministic 1-cycle latency simplifies hardware protocol validation, while ISP allows field upgrades when adding new channel bonding features. Its commercial 0-70 °C range suits temperature-controlled central-office shelves, and the TQFP-100 package is compatible with automated optical-inspection assembly lines used by contract manufacturers.
Recommandé
Embedded Computing Glue Logic in Single-Board Computers
The EPM3128ATC100-10N integrates custom peripheral interfaces on Single-Board Computers (SBCs), where it bridges between ARM/SoC memory buses and legacy parallel ports, IDE interfaces, or custom FPGA mezzanine cards. Its 10 ns tPD adds less than one bus cycle of wait-state overhead at 100 MHz, and the 80 I/O pins handle simultaneous chip-select generation, interrupt aggregation, and GPIO expansion. The CPLD's 2500 usable gates give SBC designers headroom for last-minute feature additions without respinning the PCB.
Recommandé
White-Goods Motor Control and Appliance Logic
The EPM3128ATC100-10N is widely deployed in washing machines, dishwashers, and HVAC control boards as the central sequencer for brushless DC motor commutation and safety interlocks. Its non-volatile EEPROM configuration boots the appliance into a known state even after multi-day power loss, and the 80 I/O pins drive triac-fired heater banks, relay coils, and Hall-effect sensor inputs concurrently. The TQFP-100 footprint survives wave-solder-compatible reflow profiles used by high-volume appliance contract manufacturers.
Recommandé
Test & Measurement Equipment Front-End Logic
Test instruments use the EPM3128ATC100-10N to implement reconfigurable front-end routing matrices, trigger pattern generators, and scan-chain multiplexers. Its IEEE Std. 1532 ISP interface lets manufacturers ship instruments with field-upgradable trigger logic, extending product lifecycles without board rework. The 3.3 V/2.5 V VCCIO flexibility simplifies interfacing with modern ADCs and DACs while the 80 I/O count comfortably handles 32-channel multiplexer banks typical of mid-range oscilloscopes and data-acquisition systems.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPM3128ATC100-10N — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPM3128ATC100-10 | EPM3128ATC100-7N | EPM3128AFC256-7N |
|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Macro Cells | 128 | 128 | 128 | 128 |
| User I/O | 80 | 80 | 80 | 80 |
| tPD (ns) | 10 ns | 10 ns | 7 ns (-30%) | 7 ns (-30%) |
| VCCINT | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| VCCIO Options | 3.3 V / 2.5 V | 3.3 V / 2.5 V | 3.3 V / 2.5 V | 3.3 V / 2.5 V |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
| ISP Standard | IEEE Std. 1532 | IEEE Std. 1532 | IEEE Std. 1532 | IEEE Std. 1532 |
| Lifecycle Status | NRND | NRND | NRND | NRND |
Principaux différenciateurs
- Non-volatile EEPROM configuration enables instant-on operation (vs SRAM-based FPGAs (e.g., Cyclone series))
- Deterministic 10 ns pin-to-pin propagation delay (vs Microcontroller-based glue logic)
- IEEE Std. 1532-compliant ISP eliminates external programmer (vs Legacy bipolar PALs (e.g., PALCE16V8))
- Dual VCCIO bank flexibility (3.3 V / 2.5 V) (vs Single-supply CPLDs (e.g., MAX 7000S legacy))
Notes de conception
Estimated: at VCCINT = 3.3 V and 80 I/O simultaneously switching at 5 MHz with 25 mA load per pin, the device core plus I/O current draw is approximately 80-120 mA. Use a 100 nF ceramic decoupling capacitor on every VCCINT pin and a 10 µF bulk capacitor near the package to suppress switching transients. Place decoupling capacitors within 3 mm of the supply pins to minimize inductance; vias to internal power planes must be at least 0.3 mm diameter for low ESL.
The 100-pin TQFP package (14 x 14 mm body, 0.5 mm pitch) requires a 4-layer PCB with continuous power and ground planes under the device to manage simultaneous switching noise. Route JTAG signals (TDI/TDO/TMS/TCK) as a daisy chain with 10 kΩ pull-ups on TMS and TCK, and place a 4.7 kΩ series terminator on TDO if the chain length exceeds 100 mm. For ISP chains longer than 4 devices, use a star topology to avoid signal integrity issues during programming.
Estimated: the TQFP-100 has a θJA of approximately 35-40 °C/W on a 4-layer JEDEC test board. At maximum operating ambient (70 °C commercial) and worst-case power dissipation of ~1 W (core + I/O), junction temperature rise is 35-40 °C above ambient, leaving 35-40 °C margin to the datasheet maximum Tj of 150 °C. For enclosed industrial enclosures with ambient above 50 °C, add thermal vias under the exposed pad region and ensure minimum 50 mm² of copper pour on both top and bottom layers.
Do not leave JTAG pins floating: TCK and TMS must be pulled to logic high through 10 kΩ resistors to keep the TAP controller in a defined state during power-up, otherwise the device may enter random JTAG states. VCCIO must ramp up before or simultaneously with VCCINT to prevent I/O latch-up; use a common power-sequencer IC or RC delay on the VCCINT rail if independent rails are used. Never exceed the maximum JTAG TCK frequency of 10 MHz for in-system programming.
Informations de conformité
RoHS compliance indicated by the -N suffix per Altera/Intel ordering information. REACH SVHC declaration available from Intel product compliance page. Not AEC-Q100 qualified - this is a commercial-grade part intended for industrial and consumer applications. Conflict-minerals declaration compliant per Intel Conflict-Free Smelter Program.
