EPM7128AETC100-10 - MAX 7000A CPLD 128MC 10ns 100TQFP | Intel
Référence : EPM7128AETC100-10 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $21.69 | $21,69 |
| 10 | $19.5 | $195,00 |
| 100 | $17.3 | $1 730,00 |
| 500 | $15.4 | $7 700,00 |
| 1 000 | $13.85 | $13 850,00 |
EPM7128AETC100-10 Présentation
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the instant-on characteristics of PAL/GAL architectures with the density of small FPGAs. Within the broader programmable logic hierarchy, CPLDs sit between simple SPLDs and FPGAs, offering deterministic timing, low power, and in-system programmability via EEPROM or flash cells. The MAX 7000A family targets glue-logic, bus-interface, and state-machine replacement roles where deterministic propagation delay and high drive strength matter more than raw logic density.
Key features include 128 macrocells organized into 8 Logic Array Blocks (LABs), 100% factory-tested operation across commercial and industrial temperature ranges, an in-system programmable (ISP) EEPROM process for fast revision changes, and JTAG-compatible IEEE 1149.1 boundary-scan test support. The device operates from a 3.3 V core supply with 5.0 V-tolerant I/O, easing migration from legacy 5 V MAX 7000S designs. Pin-compatible footprint with the 5.0 V MAX 7000S family allows drop-in upgrades in many boards.
Architecturally, each macrocell contains a programmable AND/OR array plus a flipflop, with a product-term allocator that distributes up to 32 product terms per macrocell. The EPM7128AETC100-10 achieves a typical internal register-to-register toggle frequency above 150 MHz and a maximum pin-to-pin delay (tPD) of 10 ns, making it suitable for high-speed address decoding and bus arbitration.
Typical applications include high-speed address decoding, peripheral glue logic, bus-width adaptation (e.g., 8-bit to 16-bit multiplexing), state-machine implementation, and digital control in industrial, telecom, and embedded systems. It is widely used in legacy designs as a replacement for discrete TTL/CMOS gate arrays.
A design tip: route global clocks to dedicated GCLK pins to minimize skew, and use the JTAG chain for both ISP and boundary-scan test. Pin compatibility with MAX 7000S devices such as the EPM7128SQC100 simplifies migration from 5 V to 3.3 V systems.
This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet alone.
Alternatives de remplacement direct pour EPM7128AETC100-10 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPM7128AETC100-10 (même facteur de forme et même empreinte) — différant par Package, Operating Temperature, Family, Process Technology, JTAG Support.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPM7128AETC100-10N
✅ Remplacement direct✓ En stock
$9.95 / unité
Voir la fiche technique →EPM7128AEFC100-5
✅ Remplacement direct✓ En stock
$79.5 / unité
Voir la fiche technique →EPM7128AETC100-7
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EPM570T100C5N
✅ Remplacement direct✓ En stock
$10.2 / unité
Voir la fiche technique →EPM240T100C5N
✅ Remplacement direct✓ En stock
$4.65 / unité
Voir la fiche technique →EPM7128AETI100-7
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$30.1 / unité
Voir la fiche technique →EPM7128AETC100-10 Valeurs maximales et caractéristiques électriques
| Family | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| User I/Os | 84 |
| Usable Gates | 2.5K |
| Logic Array Blocks (LABs) | 8 |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Supply Voltage (Core) | 3.3 V |
| I/O Tolerance | 5.0 V tolerant |
| Program Technology | EEPROM (in-system programmable) |
| Boîtier | 100-pin TQFP (ET) |
| Température de fonctionnement | -40C to +85C (commercial/industrial) |
| JTAG Support | IEEE 1149.1 boundary-scan |
| Statut RoHS | Compliant |
| Statut du cycle de vie | Obsolete (migrate to MAX II or MAX V) |
Configuration des broches de EPM7128AETC100-10
| Broche 1 | GND — Ground |
| Broche 2 | I/O — User I/O pin (LAB A) |
| Broche 3 | I/O — User I/O pin (LAB A) |
| Broche 4 | I/O — User I/O pin (LAB A) |
| Broche 5 | I/O — User I/O pin (LAB A) |
| Broche 6 | I/O — User I/O pin (LAB A) |
| Broche 7 | I/O — User I/O pin (LAB A) |
| Broche 8 | I/O — User I/O pin (LAB A) |
| Broche 9 | I/O — User I/O pin (LAB A) |
| Broche 10 | I/O — User I/O pin (LAB A) |
| Broche 11 | GND — Ground |
| Broche 12 | I/O — User I/O pin (LAB A) |
| Broche 13 | I/O — User I/O pin (LAB A) |
| Broche 14 | I/O — User I/O pin (LAB A) |
| Broche 15 | TDI — JTAG Test Data In |
| Broche 16 | TMS — JTAG Test Mode Select |
| Broche 17 | TCK — JTAG Test Clock |
| Broche 18 | I/O — User I/O pin (LAB B) |
| Broche 19 | I/O — User I/O pin (LAB B) |
| Broche 20 | I/O — User I/O pin (LAB B) |
| Broche 21 | VCC — 3.3 V core supply |
| Broche 22 | I/O — User I/O pin (LAB B) |
| Broche 23 | I/O — User I/O pin (LAB B) |
| Broche 24 | I/O — User I/O pin (LAB B) |
| Broche 25 | GCLK2 — Global clock input 2 |
| Broche 26 | I/O — User I/O pin (LAB B) |
| Broche 27 | OE2 — Global output enable 2 |
| Broche 28 | I/O — User I/O pin (LAB B) |
| Broche 29 | GND — Ground |
| Broche 30 | I/O — User I/O pin (LAB C) |
| Broche 31 | I/O — User I/O pin (LAB C) |
| Broche 32 | I/O — User I/O pin (LAB C) |
| Broche 33 | I/O — User I/O pin (LAB C) |
| Broche 34 | I/O — User I/O pin (LAB C) |
| Broche 35 | I/O — User I/O pin (LAB C) |
| Broche 36 | I/O — User I/O pin (LAB C) |
| Broche 37 | I/O — User I/O pin (LAB C) |
| Broche 38 | I/O — User I/O pin (LAB C) |
| Broche 39 | GND — Ground |
| Broche 40 | I/O — User I/O pin (LAB C) |
| Broche 41 | I/O — User I/O pin (LAB C) |
| Broche 42 | I/O — User I/O pin (LAB C) |
| Broche 43 | I/O — User I/O pin (LAB D) |
| Broche 44 | I/O — User I/O pin (LAB D) |
| Broche 45 | I/O — User I/O pin (LAB D) |
| Broche 46 | I/O — User I/O pin (LAB D) |
| Broche 47 | VCC — 3.3 V core supply |
| Broche 48 | I/O — User I/O pin (LAB D) |
| Broche 49 | I/O — User I/O pin (LAB D) |
| Broche 50 | I/O — User I/O pin (LAB D) |
| Broche 51 | GCLK3 — Global clock input 3 |
| Broche 52 | I/O — User I/O pin (LAB D) |
| Broche 53 | OE1 — Global output enable 1 |
| Broche 54 | I/O — User I/O pin (LAB D) |
| Broche 55 | I/O — User I/O pin (LAB E) |
| Broche 56 | GND — Ground |
| Broche 57 | I/O — User I/O pin (LAB E) |
| Broche 58 | I/O — User I/O pin (LAB E) |
| Broche 59 | I/O — User I/O pin (LAB E) |
| Broche 60 | I/O — User I/O pin (LAB E) |
| Broche 61 | I/O — User I/O pin (LAB E) |
| Broche 62 | I/O — User I/O pin (LAB E) |
| Broche 63 | I/O — User I/O pin (LAB E) |
| Broche 64 | I/O — User I/O pin (LAB E) |
| Broche 65 | I/O — User I/O pin (LAB E) |
| Broche 66 | GND — Ground |
| Broche 67 | I/O — User I/O pin (LAB F) |
| Broche 68 | I/O — User I/O pin (LAB F) |
| Broche 69 | I/O — User I/O pin (LAB F) |
| Broche 70 | I/O — User I/O pin (LAB F) |
| Broche 71 | I/O — User I/O pin (LAB F) |
| Broche 72 | VCC — 3.3 V core supply |
| Broche 73 | I/O — User I/O pin (LAB F) |
| Broche 74 | I/O — User I/O pin (LAB F) |
| Broche 75 | I/O — User I/O pin (LAB F) |
| Broche 76 | I/O — User I/O pin (LAB F) |
| Broche 77 | GCLK1 — Global clock input 1 |
| Broche 78 | I/O — User I/O pin (LAB G) |
| Broche 79 | OE0/GCLK4 — Global output enable 0 / Global clock 4 |
| Broche 80 | I/O — User I/O pin (LAB G) |
| Broche 81 | I/O — User I/O pin (LAB G) |
| Broche 82 | I/O — User I/O pin (LAB G) |
| Broche 83 | GND — Ground |
| Broche 84 | I/O — User I/O pin (LAB G) |
| Broche 85 | I/O — User I/O pin (LAB G) |
| Broche 86 | I/O — User I/O pin (LAB G) |
| Broche 87 | I/O — User I/O pin (LAB H) |
| Broche 88 | I/O — User I/O pin (LAB H) |
| Broche 89 | I/O — User I/O pin (LAB H) |
| Broche 90 | I/O — User I/O pin (LAB H) |
| Broche 91 | I/O — User I/O pin (LAB H) |
| Broche 92 | I/O — User I/O pin (LAB H) |
| Broche 93 | VCC — 3.3 V core supply |
| Broche 94 | I/O — User I/O pin (LAB H) |
| Broche 95 | I/O — User I/O pin (LAB H) |
| Broche 96 | I/O — User I/O pin (LAB H) |
| Broche 97 | I/O — User I/O pin (LAB H) |
| Broche 98 | TDO — JTAG Test Data Out |
| Broche 99 | I/O — User I/O pin (LAB H) |
| Broche 100 | GND — Ground |
Applications typiques
EPM7128AETC100-10 convient pour 7 applications: High-Speed Address Decoding, Bus Interface Glue Logic, State Machine Controller, Peripheral Chip Select Generator, Legacy Board Replacement and Repair, Digital Signal Conditioning and Timing, Industrial Protocol Bridging.
High-Speed Address Decoding
The EPM7128AETC100-10 is well suited for high-speed address decoding in microprocessor and DSP-based systems. Its 10 ns pin-to-pin propagation delay and 84 user I/Os allow decoding of multi-bank memory maps and chip-select logic for multiple peripherals in parallel, eliminating the propagation-delay skew of discrete 74LS/74F TTL gates. Place the CPLD close to the processor bus and use dedicated GCLK pins for synchronous enable logic. Compared to discrete gates, this part reduces board area, simplifies revision changes via JTAG ISP, and avoids timing-skew bugs that plague multi-chip decoder trees.
Recommandé
Bus Interface Glue Logic
Use the EPM7128AETC100-10 as bus interface glue between microprocessors, memory, and peripherals that mix 3.3 V and 5 V signaling. Its 5 V-tolerant I/Os accept legacy 5 V inputs while operating from a 3.3 V core, eliminating external level-shifters. With 128 macrocells the device can implement 8-bit-to-16-bit multiplexers, FIFO flags, wait-state generators, and bus-arbiter state machines in a single chip. The 100-pin TQFP footprint keeps traces short, minimizing EMI and signal-integrity issues on multi-MHz buses. For new designs, EPM570T100C5N provides more headroom at the same footprint.
Recommandé
State Machine Controller
The 128 macrocells and 8 LABs of the EPM7128AETC100-10 comfortably host large Moore/Mealy state machines for industrial control, instrumentation, and protocol conversion. Each macrocell includes a dedicated flip-flop and product-term allocator, enabling dense encoding without routing bottlenecks. The EEPROM process provides instant-on configuration on power-up, critical for deterministic startup in safety-relevant controllers. Designers can implement a complete UART, I2C, or SPI state machine in this single CPLD and still have room for auxiliary glue. JTAG boundary-scan simplifies production test.
Recommandé
Peripheral Chip Select Generator
The EPM7128AETC100-10 excels as a peripheral chip-select generator in embedded systems with multiple memory and I/O devices. By integrating up to a dozen chip-select decoders, it replaces discrete 74HC138/139 demultiplexers while adding programmability for late-stage address-map changes. The 10 ns tPD ensures the chip-select signal arrives well within typical memory access cycles (50-100 ns), avoiding wait states. ISP via JTAG lets you re-target chip-selects during board bring-up without re-spinning the PCB. Industrial temperature grade supports deployment in factory automation.
Recommandé
Legacy Board Replacement and Repair
The EPM7128AETC100-10 is most commonly deployed as a maintenance and repair part for legacy boards originally designed around the MAX 7000A family. Its pin-compatible footprint with EPM7128AETC100-10N (lead-free), EPM7128AEFC100-5, and EPM7128SQC100-10 lets field engineers substitute equivalent parts without board rework. EEPROM-based ISP enables on-site firmware upgrades through the JTAG header. Although the part is marked obsolete by Intel, distributor stock remains available (e.g., Heisener reports 32,364 pieces as of 2026-09-12). For new designs, migrate to MAX II or MAX V.
Recommandé
Digital Signal Conditioning and Timing
The EPM7128AETC100-10 is useful for digital signal conditioning and timing alignment in mixed-signal boards, where it can deskew clocks, generate programmable delays, and re-time asynchronous handshake signals. The 8 LABs and 128 macrocells are enough to host multi-channel delay lines, pulse generators, and watchdog timers. With 5 V-tolerant inputs, the device can safely interface to legacy 5 V sensors or ASICs while presenting clean 3.3 V outputs to downstream logic. For higher-speed timing applications, the 5 ns EPM7128AEFC100-5 variant halves the propagation delay.
Recommandé
Industrial Protocol Bridging
Industrial protocol bridging is a strong fit for the EPM7128AETC100-10, where it can convert between UART, SPI, I2C, parallel, and proprietary fieldbus formats. Its deterministic 10 ns tPD and 128 macrocells support full-duplex protocol engines at modest baud rates without jitter. EEPROM ISP lets field engineers update protocol firmware via JTAG without removing the board from service. Industrial temperature grade (-40C to +85C) supports deployment in factory-floor cabinets and outdoor enclosures. For higher baud rates or more channels, the EPM570T100C5N provides 4x the macrocell budget.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPM7128AETC100-10 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPM7128AETC100-10N | EPM7128AEFC100-5 | EPM7128AETC100-7 | EPM570T100C5N | EPM240T100C5N | EPM7128AETI100-7 |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 100-pin TQFP | 100-pin TQFP - same | 100-pin TQFP - same | 100-pin TQFP - same | 100-pin TQFP - same | 100-pin TQFP - same | 100-pin TQFP - same |
| Family | MAX 7000A | MAX 7000A - same | MAX 7000A - same | MAX 7000A - same | MAX II - newer | MAX II - newer | MAX 7000A - same |
| Macrocells | 128 | 128 - same | 128 - same | 128 - same | 570 (4.4x) | 240 (1.9x) | 128 - same |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns - same | 5 ns (faster) | 7 ns (faster) | 5 ns (faster) | 5 ns (faster) | 7 ns (faster) |
| User I/Os | 84 | 84 - same | 84 - same | 84 - same | 76 | 80 | 84 - same |
| Core Voltage | 3.3 V | 3.3 V - same | 3.3 V - same | 3.3 V - same | 3.3 V - same | 3.3 V - same | 3.3 V - same |
| Operating Temperature | -40C to +85C (commercial) | -40C to +85C - same | -40C to +85C - same | -40C to +85C - same | -40C to +85C - same | -40C to +85C - same | -40C to +100C (industrial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Active | Active | Obsolete |
Principaux différenciateurs
- Obsolete status with active drop-in alternatives (vs EPM7128AETC100-10N)
- Lower speed grade available with cost savings (vs EPM7128AEFC100-5)
- Migration path to active-lifecycle MAX II (vs EPM570T100C5N)
- Pin-compatible 5 V upgrade option available (vs EPM7128SQC100-10)
Notes de conception
The EPM7128AETC100-10 requires a clean 3.3 V core supply with decoupling capacitors placed as close as possible to each VCC pin. According to the MAX 7000A datasheet, place one 0.1 uF ceramic decoupling cap per VCC pin and a single 10 uF bulk capacitor near the package. The device has 6 VCC pins and 6 GND pins distributed around the 100-pin TQFP - all must be connected for stable operation. Insufficient decoupling can cause JTAG programming failures or logic errors at high toggle rates.
Route all four global clock inputs (GCLK1-GCLK4) on dedicated short, matched-length traces to minimize clock skew across LABs. The EPM7128AETC100-10 provides 4 global clocks and 4 global output enables (OE0-OE3) - using dedicated pins avoids internal routing delay. According to Altera MAX 7000A design guidelines, keep high-speed I/O signals away from the JTAG pins (TDI/TDO/TMS/TCK) and route the JTAG chain through a 4.7 kohm pull-up on TMS and TCK to keep the boundary-scan state machine in reset during power-up.
Do not confuse the EPM7128AETC100-10 (3.3 V MAX 7000A) with the pin-compatible EPM7128SQC100-10 (5.0 V MAX 7000S). Applying 5 V to VCC on the EPM7128AETC100-10 will damage the device. Also note that the 'N' suffix (EPM7128AETC100-10N) indicates lead-free RoHS compliance - the bare EPM7128AETC100-10 has SnPb die attach and may not meet RoHS requirements for new products. JTAG ISP requires a 10-pin or ByteBlaster-compatible header; do not omit pull-ups on TMS and TCK or the device may enter unwanted boundary-scan states at power-up.
Informations de conformité
Bare EPM7128AETC100-10 uses SnPb die attach (non-RoHS). The N-suffix variant (EPM7128AETC100-10N) is lead-free RoHS compliant. AEC-Q100 not applicable - this is a commercial/industrial-grade programmable logic device, not an automotive qualified part.
