Intel

EPM9320ALI84-10 - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Intel

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5.0 V Vdss 84-pin PLCC (Plastic Leaded Chip Carrier) Package 144 MHz Speed CMOS EEPROM Memory

À partir de $19.95 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-13

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$38.5	$38,50
10	$34.2	$342,00
100	$28.75	$2 875,00
500	$24.1	$12 050,00
1 000	$19.95	$19 950,00

ℹ️ Tous les prix sont en USD

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EPM9320ALI84-10 Présentation

The Intel (formerly Altera) EPM9320ALI84-10 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, fabricated on an advanced CMOS technology. The device provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz, all housed in an 84-pin PLCC package. It delivers 320 macrocells and is supported by 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface.

A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single die with a programmable interconnect matrix, sitting hierarchically between simple SPLDs/CPLDs and FPGAs in the programmable logic taxonomy: SPLD < CPLD < FPGA < programmable logic < semiconductor. The MAX architecture specifically uses a Multiple Array MatriX (MAX) interconnect that delivers predictable timing, a critical advantage over SRAM-based FPGAs for glue-logic and bus-interface roles where deterministic propagation delay matters.

Key specifications of the EPM9320ALI84-10 include 320 macrocells, 84 user I/O pins, 10 ns pin-to-pin combinatorial delay (Tpd1), 144 MHz maximum counter frequency, and 5.0V VCC operation. The device also features four dedicated inputs, JTAG boundary-scan test compliance per IEEE 1149.1, and an industrial operating temperature range of -40C to +85C suitable for harsh environments.

Architecturally, the MAX 9000 family integrates PAL-like logic array blocks (LABs) with a high-speed programmable interconnect array (PIA). The EEPROM process technology provides non-volatile configuration that retains the design pattern through power cycles without an external boot PROM, simplifying board design and reducing bill-of-materials cost.

Typical applications include high-speed bus interfacing and address decoding in embedded systems, peripheral glue logic in telecommunications equipment, industrial control system logic integration, and replacement of multiple discrete 22V10/PAL/GAL devices in legacy board designs. The deterministic timing also makes it suitable for state-machine controller and protocol-bridge implementations.

When designing with this part, note that -10 grade denotes 10 ns tpd; slower (-15, -20) and faster (-7) grades are available as pin-compatible drop-in replacements within the same 84-PLCC footprint. ISP via JTAG requires a 5V-tolerant TCK/TMS/TDI/TDO chain wired to a programming header or boundary-scan controller.

This page synthesizes distributor pricing, drop-in same-family alternatives, JTAG programming guidance, and thermal/PCB layout notes that are not consolidated in the manufacturer datasheet alone.

Alternatives de remplacement direct pour EPM9320ALI84-10 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPM9320ALI84-10 (même facteur de forme et même empreinte) — différant par Package, Mounting Type, Process Technology, Architecture, Propagation Delay (tPD).

EPM9320ALC84-10

Intel

Package: 84-pin PLCC (J-Lead)

Mounting Type: Surface Mount / Through-Hole (PLCC socket)

Architecture: MAX (Multiple Array MatriX) with FastTrack Interconnect