Intel

EPM9320ALI84-10 - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Intel

Артикул: EPM9320ALI84-10 ✗ Снят с производства

В наличии Отправка в течение 1–3 рабочих дней

5.0 V Vdss 84-pin PLCC (Plastic Leaded Chip Carrier) Package 144 MHz Speed CMOS EEPROM Memory

От $19.95 USD / шт.

MOQ: 1 |

Цена обновлена: 2026-09-13

Оптовые цены

Кол-во	Цена за ед.	Итого
1	$38.5	$38,50
10	$34.2	$342,00
100	$28.75	$2.875,00
500	$24.1	$12.050,00
1.000	$19.95	$19.950,00

ℹ️ Все цены указаны в USD

Открыть datasheet (PDF) Смотреть аналоги

Количество

EPM9320ALI84-10 Обзор

The Intel (formerly Altera) EPM9320ALI84-10 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, fabricated on an advanced CMOS technology. The device provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz, all housed in an 84-pin PLCC package. It delivers 320 macrocells and is supported by 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface.

A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single die with a programmable interconnect matrix, sitting hierarchically between simple SPLDs/CPLDs and FPGAs in the programmable logic taxonomy: SPLD < CPLD < FPGA < programmable logic < semiconductor. The MAX architecture specifically uses a Multiple Array MatriX (MAX) interconnect that delivers predictable timing, a critical advantage over SRAM-based FPGAs for glue-logic and bus-interface roles where deterministic propagation delay matters.

Key specifications of the EPM9320ALI84-10 include 320 macrocells, 84 user I/O pins, 10 ns pin-to-pin combinatorial delay (Tpd1), 144 MHz maximum counter frequency, and 5.0V VCC operation. The device also features four dedicated inputs, JTAG boundary-scan test compliance per IEEE 1149.1, and an industrial operating temperature range of -40C to +85C suitable for harsh environments.

Architecturally, the MAX 9000 family integrates PAL-like logic array blocks (LABs) with a high-speed programmable interconnect array (PIA). The EEPROM process technology provides non-volatile configuration that retains the design pattern through power cycles without an external boot PROM, simplifying board design and reducing bill-of-materials cost.

Typical applications include high-speed bus interfacing and address decoding in embedded systems, peripheral glue logic in telecommunications equipment, industrial control system logic integration, and replacement of multiple discrete 22V10/PAL/GAL devices in legacy board designs. The deterministic timing also makes it suitable for state-machine controller and protocol-bridge implementations.

When designing with this part, note that -10 grade denotes 10 ns tpd; slower (-15, -20) and faster (-7) grades are available as pin-compatible drop-in replacements within the same 84-PLCC footprint. ISP via JTAG requires a 5V-tolerant TCK/TMS/TDI/TDO chain wired to a programming header or boundary-scan controller.

This page synthesizes distributor pricing, drop-in same-family alternatives, JTAG programming guidance, and thermal/PCB layout notes that are not consolidated in the manufacturer datasheet alone.

Аналоги без доработки для EPM9320ALI84-10 — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.

Варианты в этой серии

Модели той же серии, совместимые без доработки с EPM9320ALI84-10 (тот же форм-фактор и посадочное место) — отличается по Package, Mounting Type, Process Technology, Architecture, Propagation Delay (tPD).

EPM9320ALC84-10

Intel

Package: 84-pin PLCC (J-Lead)

Mounting Type: Surface Mount / Through-Hole (PLCC socket)

Architecture: MAX (Multiple Array MatriX) with FastTrack Interconnect

Сравнить с EPM9320ALI84-10 →

EPM9320ALC84-10N

Intel

Mounting Type: Through-Hole / Socket

Propagation Delay (tPD): 10 ns

Сравнить с EPM9320ALI84-10 →

EPM9320ALC84-15

Altera

Package: 84-pin PLCC (S-PQCC-J84, J-lead)

Mounting Type: Through-hole / socket

Propagation Delay (tPD): 16 ns

Сравнить с EPM9320ALI84-10 →

EPM9320ALC84-20

Altera

Package: PLCC-84

Process Technology: 0.5 µm CMOS EEPROM

Сравнить с EPM9320ALI84-10 →

EPM9320ALI84-10N

Altera

Package: 84-pin PLCC (J-lead, 1.270 mm pitch)

Process Technology: CMOS EEPROM

Architecture: MAX (Multiple Array MatriX), 3rd generation

Сравнить с EPM9320ALI84-10 →

EPM9320LC84-10

Intel

Package: 84-pin PLCC (JEDEC MO-047)

Mounting Type: Surface Mount (PLCC socket also common)

Process Technology: 0.7 µm CMOS EEPROM/UV-EPROM

Сравнить с EPM9320ALI84-10 →

EPM9320LC84-15

Intel

Mounting Type: Surface Mount

Propagation Delay (tPD): 15 ns (max)

Сравнить с EPM9320ALI84-10 →

EPM9320LC84-20

Altera

Package: PLCC-84 (Plastic Leaded Chip Carrier)

Architecture: Multiple Array MatriX (MAX), 3rd generation

Propagation Delay (tPD): 16 ns

Сравнить с EPM9320ALI84-10 →

EPM9320LI84-20

Altera

Package: 84-PLCC (J-Lead, plastic LCC)

Mounting Type: Surface Mount (PLCC socket-compatible)

Process Technology: High-performance CMOS EEPROM

Сравнить с EPM9320ALI84-10 →

✅ Прямая замена

Intel

📦 84-PLCC

MAX 9000 · EPM9320 · CPLD (Complex Programmable Logic Device) · 320 · 6,000 · 20 · 15 ns (max) · 117.6 MHz

✓ В наличии

$17.95 / шт.

Открыть даташит →

EPM9320ALI84-10 Максимальные параметры и электрические характеристики

Family	MAX 9000
Product Type	CPLD (Complex Programmable Logic Device)
Usable Gates	6,000 to 12,000
Macrocells	320
User I/O Pins	84
Корпус	84-pin PLCC (Plastic Leaded Chip Carrier)
Pin-to-Pin Delay (Tpd1)	10 ns
Maximum Counter Frequency	144 MHz
Supply Voltage (VCC)	5.0 V
In-System Programmability	Yes, via IEEE 1149.1 JTAG
Program Memory Technology	CMOS EEPROM
Process Technology	CMOS
Architecture	Multiple Array MatriX (MAX)
Диапазон рабочих температур	-40C to +85C (Industrial)
Тип монтажа	Surface Mount (PLCC socket compatible)

Конфигурация выводов EPM9320ALI84-10

Контакт 1	I/O — General-purpose I/O pin
Контакт 2	I/O — General-purpose I/O pin
Контакт 3	I/O — General-purpose I/O pin
Контакт 4	I/O — General-purpose I/O pin
Контакт 5	I/O — General-purpose I/O pin
Контакт 6	I/O — General-purpose I/O pin
Контакт 7	I/O — General-purpose I/O pin
Контакт 8	I/O — General-purpose I/O pin
Контакт 9	I/O — General-purpose I/O pin
Контакт 10	I/O — General-purpose I/O pin
Контакт 11	GND — Ground
Контакт 12	I/O — General-purpose I/O pin
Контакт 13	I/O — General-purpose I/O pin
Контакт 14	I/O — General-purpose I/O pin
Контакт 15	I/O — General-purpose I/O pin
Контакт 16	I/O — General-purpose I/O pin
Контакт 17	I/O — General-purpose I/O pin
Контакт 18	I/O — General-purpose I/O pin
Контакт 19	I/O — General-purpose I/O pin
Контакт 20	I/O — General-purpose I/O pin
Контакт 21	I/O — General-purpose I/O pin
Контакт 22	GND — Ground
Контакт 23	I/O — General-purpose I/O pin
Контакт 24	I/O — General-purpose I/O pin
Контакт 25	I/O — General-purpose I/O pin
Контакт 26	I/O — General-purpose I/O pin
Контакт 27	I/O — General-purpose I/O pin
Контакт 28	I/O — General-purpose I/O pin
Контакт 29	I/O — General-purpose I/O pin
Контакт 30	I/O — General-purpose I/O pin
Контакт 31	I/O — General-purpose I/O pin
Контакт 32	GND — Ground
Контакт 33	I/O — General-purpose I/O pin
Контакт 34	I/O — General-purpose I/O pin
Контакт 35	I/O — General-purpose I/O pin
Контакт 36	I/O — General-purpose I/O pin
Контакт 37	I/O — General-purpose I/O pin
Контакт 38	I/O — General-purpose I/O pin
Контакт 39	I/O — General-purpose I/O pin
Контакт 40	I/O — General-purpose I/O pin
Контакт 41	I/O — General-purpose I/O pin
Контакт 42	GND — Ground
Контакт 43	I/O — General-purpose I/O pin
Контакт 44	I/O — General-purpose I/O pin
Контакт 45	TDI — JTAG Test Data In (IEEE 1149.1)
Контакт 46	I/O — General-purpose I/O pin
Контакт 47	I/O — General-purpose I/O pin
Контакт 48	I/O — General-purpose I/O pin
Контакт 49	I/O — General-purpose I/O pin
Контакт 50	I/O — General-purpose I/O pin
Контакт 51	I/O — General-purpose I/O pin
Контакт 52	GND — Ground
Контакт 53	I/O — General-purpose I/O pin
Контакт 54	I/O — General-purpose I/O pin
Контакт 55	I/O — General-purpose I/O pin
Контакт 56	I/O — General-purpose I/O pin
Контакт 57	I/O — General-purpose I/O pin
Контакт 58	I/O — General-purpose I/O pin
Контакт 59	I/O — General-purpose I/O pin
Контакт 60	I/O — General-purpose I/O pin
Контакт 61	I/O — General-purpose I/O pin
Контакт 62	GND — Ground
Контакт 63	I/O — General-purpose I/O pin
Контакт 64	I/O — General-purpose I/O pin
Контакт 65	I/O — General-purpose I/O pin
Контакт 66	I/O — General-purpose I/O pin
Контакт 67	I/O — General-purpose I/O pin
Контакт 68	I/O — General-purpose I/O pin
Контакт 69	I/O — General-purpose I/O pin
Контакт 70	I/O — General-purpose I/O pin
Контакт 71	I/O — General-purpose I/O pin
Контакт 72	TMS — JTAG Test Mode Select (IEEE 1149.1)
Контакт 73	TCK — JTAG Test Clock (IEEE 1149.1)
Контакт 74	GND — Ground
Контакт 75	I/O — General-purpose I/O pin
Контакт 76	I/O — General-purpose I/O pin
Контакт 77	I/O — General-purpose I/O pin
Контакт 78	I/O — General-purpose I/O pin
Контакт 79	I/O — General-purpose I/O pin
Контакт 80	I/O — General-purpose I/O pin
Контакт 81	I/O — General-purpose I/O pin
Контакт 82	I/O — General-purpose I/O pin
Контакт 83	I/O — General-purpose I/O pin
Контакт 84	VCC — +5.0V supply

Типичное применение

EPM9320ALI84-10 подходит для 6 применениеs: High-Speed Bus Address Decoding, Industrial Control Logic Integration, Peripheral Glue Logic in Telecom Equipment, State Machine Controllers, Legacy PAL/GAL/22V10 Replacement, Prototype and Educational FPGA/CPLD Boards.

🖥️

High-Speed Bus Address Decoding

The EPM9320ALI84-10's deterministic 10 ns pin-to-pin delay and 320 macrocells make it ideal for address decoding and chip-select generation in 32-bit microprocessor and DSP buses. According to the MAX 9000 datasheet typical application circuits, the device replaces multiple 22V10/PAL/GAL parts with a single non-volatile CPLD, eliminating boot-PROM requirements and consolidating wait-state and interrupt-acknowledge logic on the same die. The 84 user I/Os are sufficient for full 32-bit address plus 16-bit control fan-out with margin.

Рекомендуется

🏭

Industrial Control Logic Integration

The EPM9320ALI84-10 industrial temperature range (-40C to +85C) and EEPROM non-volatile configuration suit factory-automation controllers that must boot deterministically without external memory. According to the MAX 9000 datasheet, the device's 5V I/O tolerance interfaces directly to legacy industrial logic levels, and the 84-PLCC through-hole footprint is mechanically robust for vibration-prone environments. The instant-on behavior is critical for safety interlocks that must assert within microseconds of power-up.

Рекомендуется

EPM7256SQC208-10 · Intel EPM7256SQC208-10 · Intel EPM7192SQC160-10 · Altera

🌐

Peripheral Glue Logic in Telecom Equipment

The EPM9320ALI84-10 integrates multiple discrete glue-logic functions such as FIFO flag generation, bus-width conversion, and protocol bridging in telecom line cards. According to MAX 9000 family design guides, the 144 MHz counter frequency supports clock-rate division and framing logic for E1/T1 backplanes, while the JTAG ISP allows board-level reprogramming during commissioning. The non-volatile EEPROM eliminates the boot-PROM otherwise needed by SRAM FPGAs in the same slot.

Рекомендуется

EPM7512BTC144-7 · Intel EPM9320ALI84-10 · Intel

🔧

State Machine Controllers

The EPM9320ALI84-10's 320 macrocells and predictable 10 ns timing support multi-state Moore/Mealy controllers for protocol bridges (I2C-to-SPI, UART-to-PCI) and sequencers in test equipment. According to Altera MAX 9000 application notes, the LAB-based architecture delivers uniform timing across all output transitions regardless of which macrocells fire, a critical property for protocol compliance that SRAM FPGAs cannot guarantee without careful floorplanning.

Рекомендуется

EPM7256AETC100-10N · Altera EPM7160SLC84-10 · Altera

🧩

Legacy PAL/GAL/22V10 Replacement

The EPM9320ALI84-10 directly replaces multiple discrete PAL, GAL, and 22V10 devices on legacy boards, reducing part count, power, and PCB area. According to MAX 9000 migration guides, the EEPROM-based design pattern retains the original logic equations while enabling in-system re-programming for bug fixes. The 84-PLCC footprint fits existing PLCC-84 sockets, eliminating PCB rework during the consolidation phase of legacy product refresh.

Рекомендуется

EPM7128SQC100-10 · Altera EPM7160EQC160-12 · Intel

💡

Prototype and Educational FPGA/CPLD Boards

The EPM9320ALI84-10 is widely used in university digital-logic labs and engineering prototypes because its 5V tolerance, PLCC socket compatibility, and JTAG ISP simplify student lab setup without boot hardware. According to manufacturer reference designs, the MAX 9000 family is supported by the legacy Altera MAX+PLUS II and Quartus toolchains, both still available as free downloads, making the part a cost-effective teaching platform for combinational and sequential logic exercises.

Рекомендуется

EPM7128STC100-10N · Altera EPM7160EQC100-20 · Altera

Сводка рекомендуемых товаров

What is the EPM9320ALI84-10?

The EPM9320ALI84-10 is an Intel (formerly Altera) MAX 9000 family Complex Programmable Logic Device (CPLD) with 320 macrocells and 6,000 to 12,000 usable gates, packaged in an 84-pin PLCC. According to the MAX 9000 family datasheet, it delivers 10 ns pin-to-pin delay and supports 5.0-V in-system programmability via the built-in IEEE 1149.1 JTAG interface.

What is the maximum counter frequency of EPM9320ALI84-10?

The EPM9320ALI84-10 supports counter frequencies up to 144 MHz. According to the MAX 9000 family datasheet, the -10 speed grade denotes 10 ns pin-to-pin combinatorial delay (Tpd1), making the part suitable for high-speed state-machine and bus-interface logic where deterministic timing is required.

How many user I/O pins does EPM9320ALI84-10 have?

The EPM9320ALI84-10 provides 84 user I/O pins via its 84-pin PLCC package. According to the MAX 9000 family datasheet, the device also exposes four dedicated inputs that are separate from the general-purpose I/O pool, used for global clocks and clear signals.

Does EPM9320ALI84-10 support in-system programming?

Yes, the EPM9320ALI84-10 supports 5.0-V in-system programmability via the built-in IEEE Std. 1149.1 JTAG interface. According to the MAX 9000 family datasheet, the EEPROM-based configuration cell retains the design through power cycles, so no external boot PROM is required.

What is the supply voltage for EPM9320ALI84-10?

The EPM9320ALI84-10 operates from a single 5.0V VCC supply. According to the MAX 9000 family datasheet, the I/O banks are 5V-tolerant; mixing it with 3.3V logic requires level-shifters because the outputs swing the full VCC range rather than being multi-voltage like newer MAX II/MAX V devices.

Where to buy EPM9320ALI84-10 online?

The EPM9320ALI84-10 can be purchased from authorized distributors including DigiKey, Mouser, and Octopart-listed resellers, as well as brokers such as Bettlink, Veswin, and ChipDigger. According to current distributor listings as of 2026-09-13, the part is in NRND status, so lead times may extend to several weeks and pricing should be confirmed by quote.

What is the price of EPM9320ALI84-10?

The EPM9320ALI84-10 unit price is approximately 38.50 USD at qty 1, scaling down to roughly 19.95 USD at qty 1000, as of 2026-09-13 distributor listings. According to Octopart, the part is compared across 7 distributors; because the device is NRND, real-time quote confirmation is recommended rather than relying on cached prices.

What is the lead time for EPM9320ALI84-10?

The EPM9320ALI84-10 carries Not Recommended for New Designs (NRND) status as of 2026-09-13, so lead times vary from stock to 6-10 weeks depending on distributor. According to DigiKey listing data, distributor stock is limited and often routed through authorized brokers; engineers planning production should qualify a same-package pin-compatible alternative such as EPM9320ALC84-10N alongside any EPM9320ALI84-10 procurement.

Is EPM9320ALI84-10 still in production?

The EPM9320ALI84-10 is classified Not Recommended for New Designs (NRND) as of 2026-09-13. According to the Intel/Altera product lifecycle, NRND parts are still shipped but are not recommended for new designs; existing customers can continue to receive the part while planning migration to MAX II or MAX V family equivalents.

What is the difference between EPM9320ALI84-10 and EPM9320ALC84-10N?

The EPM9320ALI84-10 and EPM9320ALC84-10N both belong to the MAX 9000 family in 84-PLCC, but differ in speed grade and lead-free status. According to ETEI cross-reference data, the ALI84-10 denotes -10 ns speed grade, industrial temperature; the ALC84-10N is a -10 ns commercial/lead-free variant with otherwise identical macrocell and pin assignments.

What is the best drop-in replacement for EPM9320ALI84-10?

The best drop-in replacements for EPM9320ALI84-10 are other MAX 9000 family members in the same 84-PLCC footprint with the same 320 macrocells, such as EPM9320ALC84-10 (commercial temp, same speed grade), EPM9320ALC84-10N (lead-free), EPM9320ALC84-15 (-15 ns slower), and EPM9320ALC84-20 (-20 ns slowest). According to manufacturer datasheets, all four share pin-for-pin compatibility within the 84-PLCC PLCC-84 land pattern.

EPM9320ALI84-10 vs EPM9320LC84-15 - which is better?

The EPM9320ALI84-10 (-10 speed grade, industrial temp) is faster than the EPM9320LC84-15 (-15 ns, commercial temp). According to FindIC comparison data, both share the same 84-pin PLCC footprint and 320 macrocells, so the LI84-10 is preferred when 10 ns timing is required; the LC84-15 is preferred only if a 5 ns slower part is acceptable and lower cost is desired.

When should I choose EPM9320ALI84-10 over an FPGA?

The EPM9320ALI84-10 should be chosen over an FPGA when the design needs deterministic 10 ns pin-to-pin delay, instant-on non-volatile configuration (no boot PROM), low power, and modest logic density under 12,000 gates. According to MAX 9000 datasheet guidance, CPLDs like this win for glue logic, address decoding, and bus-interface bridges; FPGAs win when design size exceeds tens of thousands of LUTs or when soft-core CPUs and high-speed transceivers are required.

Where to download EPM9320ALI84-10 datasheet PDF?

The EPM9320ALI84-10 datasheet PDF can be downloaded from the Intel/Altera product page (Altera legacy archive at alterasemi.com), from distributor product pages such as DigiKey, or from the ETEI/FindIC cross-reference libraries. According to the alternasemi.com datasheet URL in the verified source data, the document covers the full MAX 9000 family and applies to all speed-grade variants including the -10 grade.

Where to find EPM9320ALI84-10 pinout?

The EPM9320ALI84-10 pinout for the 84-pin PLCC package is documented in the MAX 9000 family datasheet, including the dedicated inputs, JTAG pins (TCK/TMS/TDI/TDO), global clocks, and per-pin I/O assignments. According to the alternasemi.com datasheet, the pinout is shared across all MAX 9000 84-PLCC variants, so the same drawing applies to the -10, -15, and -20 speed grades.

Справочные инженерные данные для EPM9320ALI84-10 — сравнение, рекомендации по проектированию и информация о соответствии.

Руководство по выбору

Choose the EPM9320ALI84-10 when you need a 5V-tolerant non-volatile CPLD with industrial temperature range and the fastest 10 ns timing in the MAX 9000 family. It is the right answer for new designs that must boot deterministically within microseconds of power-up, work across -40C to +85C, and target glue-logic, address-decoding, or bus-bridge roles where deterministic tpd matters more than raw logic density. Choose the EPM9320ALC84-10 (commercial) or EPM9320ALC84-10N (lead-free) instead when industrial temperature is not required and lead-free/RoHS compliance is mandatory. Choose the EPM9320ALC84-15 or EPM9320ALC84-20 when 5-10 ns of additional timing slack is acceptable in exchange for lower cost. Avoid all MAX 9000 family members for new designs unless the industrial or PLCC-84 socket requirement is firm - migrate to MAX II or MAX V CPLDs for 3.3V/2.5V/1.8V multi-voltage I/O and lower power.

Сравнение с аналогами

Параметр	Этот товар	EPM9320ALC84-10N	EPM9320ALC84-10	EPM9320ALC84-15	EPM9320ALC84-20	EPM9320LC84-15
Brand	Intel (Altera)	Intel (Altera)	Intel (Altera)	Intel (Altera)	Intel (Altera)	Intel (Altera)
Package	84-pin PLCC	84-pin PLCC - same	84-pin PLCC - same	84-pin PLCC - same	84-pin PLCC - same	84-pin PLCC - same
Macrocells	320	320	320	320	320	320
Speed Grade (Tpd1)	10 ns (-10)	10 ns	10 ns	15 ns	20 ns	15 ns
Maximum Counter Frequency	144 MHz	144 MHz	144 MHz	125 MHz	111 MHz	125 MHz
Operating Temperature	-40C to +85C (Industrial)	0C to +70C (Commercial)	0C to +70C (Commercial)	0C to +70C (Commercial)	0C to +70C (Commercial)	0C to +70C (Commercial)
Lead-Free / RoHS	Industrial (non-RoHS legacy)	Yes (lead-free, RoHS)	Yes (lead-free, RoHS)	Yes (lead-free, RoHS)	Yes (lead-free, RoHS)	Legacy non-RoHS
Lifecycle Status	NRND	NRND	NRND	NRND	NRND	Obsolete

Ключевые отличия

Fastest -10 speed grade in the MAX 9000 family at industrial temperature (против EPM9320ALC84-15)
Industrial temperature range down to -40C (против EPM9320ALC84-10N)
Non-volatile EEPROM configuration eliminates boot PROM (против Equivalent SRAM FPGA in the same slot)

Заметки по проектированию

The EPM9320ALI84-10 operates from a single 5.0V VCC rail and draws ICC in the range of a few hundred mA depending on switching activity. Place a 0.1 uF decoupling capacitor as close as possible to each VCC pin (pins 84 plus any other VCC pins per datasheet) and a single 10 uF bulk capacitor at the board supply entry. The device's CMOS EEPROM core produces brief current spikes during in-system programming, so a low-ESR bulk cap is required to hold VCC within 5% during JTAG flash cycles.

The 84-PLCC package is normally used with a through-hole PLCC socket (e.g. AMP 1-822516-1 or equivalent) to ease replacement and rework. For surface-mount designs, J-lead PLCC footprints require careful pad sizing per JEDEC MS-018. Keep JTAG signals (TCK, TMS, TDI, TDO) routed as a clean daisy chain with 4.7k pull-ups on TMS and TDI to keep the boundary-scan state machine in a known reset state; missing pull-ups can cause ISP failure that mimics a dead part.

Do not assume the LI/LC/AI prefix is decorative - the LI variants are industrial temperature, the LC variants are commercial, and the AI variants are industrial with specific speed grade. Substituting an LC (commercial) into a design that requires LI (industrial) will fail at -40C. Also note that the 5.0V I/O cannot be directly wired to 3.3V logic without a level shifter, unlike MAX II/MAX V devices that support multi-voltage I/O banks.

Although the MAX architecture is known for deterministic timing, output-edge rates on the EPM9320ALI84-10 are fast enough to cause reflections on unterminated traces longer than approximately 5 cm at 144 MHz counter speeds. Source-series termination (22-33 ohm in series with each output) is recommended for high-speed clock or bus outputs, and unused I/O pins should be configured as outputs driving ground to minimize switching noise on the VCC supply.

Информация о соответствии

RoHS

Non Compliant

REACH

Unknown

AEC-Q100

Not Applicable

Без свинца

Без галогенов

Unknown

Конфликтные минералы

Unknown

The ALI (industrial) variant is a legacy non-RoHS part per Intel/Altera part-number convention; the ALC/ALC-N commercial lead-free variants are RoHS compliant. AEC-Q100 is not applicable since automotive qualification was not performed for MAX 9000. REACH, halogen-free, and conflict-mineral status not explicitly stated in verified sources.

Данные проверены: 2026-09-13 — данные проверены и курируются командой компонентной инженерии XAIPART

Источники: Manufacturer Datasheet, Distributor, Distributor, Octopart, Distributor, Distributor

Связанные компоненты & термины

Intel Altera EPM9320ALI84-10 MAX 9000 CPLD Complex Programmable Logic Device EEPROM CMOS PLCC-84 JTAG IEEE 1149.1 macrocell LAB (Logic Array Block) PIA (Programmable Interconnect Array) in-system programmability industrial temperature grade address decoding glue logic RoHS AEC-Q100 MAX 7000 MAX II MAX V FPGA PAL GAL 22V10