Altera

EPM9560RC208-14 - MAX 9000 CPLD, 12K Gates, 560 Macrocells | Altera

Référence : EPM9560RC208-14 ✗ Fin de vie

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5 V Vdss 208-pin RQFP (PQFP) Package 117.6 MHz Speed EEPROM (non-volatile) Memory

À partir de $27.9 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-13

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$48.5	$48,50
10	$42	$420,00
100	$35.75	$3 575,00
250	$31.2	$7 800,00
500	$27.9	$13 950,00

ℹ️ Tous les prix sont en USD

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EPM9560RC208-14 Présentation

The Altera EPM9560RC208-14 is a member of the MAX 9000 Complex Programmable Logic Device (CPLD) family, delivering 12,000 usable gates and 560 macrocells in a 208-pin RQFP (Plastic Quad Flat Pack) package. It operates from a 5 V supply, supports propagation delay binning of 14 ns (pin-to-pin), and is built on a CMOS EEPROM process that delivers non-volatile configuration with in-system programmability via the JTAG interface.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single chip with a central interconnect matrix. In the system hierarchy, the EPM9560 sits between simple SPLDs (like classic PAL/GAL) and larger FPGAs, providing fast deterministic pin-to-pin timing, instant-on behavior (no boot PROM required), and high fan-in / fan-out glue-logic capability. The MAX 9000 family extends MAX 7000 architecture with larger Logic Array Blocks (LABs), more I/O pins, and enhanced in-system programmability (ISP) via JTAG.

Key features of the EPM9560RC208-14 include 560 macrocells distributed across 16 Logic Array Blocks, 149 user I/O pins, 12,000 usable gates, and a maximum operating frequency up to 117.6 MHz. It supports 5 V and 3.3 V mixed-voltage operation on its I/O banks and is in-system programmable through the IEEE 1149.1 JTAG boundary-scan port. The -14 speed grade provides a 14 ns pin-to-pin propagation delay and a 118 MHz internal counter frequency.

The device is implemented in 0.35 µm CMOS EEPROM technology with five programmable logic blocks (the MAX 9000 also adds I/O blocks for each pin), allowing design changes via the Altera MAX+PLUS II or Quartus development flows. The 208-pin RQFP package exposes dedicated JTAG, configuration, and global clock pins for design flexibility. Built-in EEPROM cells retain the design without external boot memory.

Typical applications include high-density glue logic in telecommunications line cards, industrial control boards, ASIC prototyping, peripheral bus interfacing (PCI bridge logic, address decoding, bus arbitration), and replacement of multiple discrete PAL/GAL devices. The fast pin-to-pin delay also suits decoder and interrupt-controller designs where deterministic timing matters.

Designers should plan for a 5 V core supply with local 0.1 µF + 10 µF decoupling near the device. The MAX 9000 architecture allows multiple MAX 9560 devices to be cascaded through the JTAG chain, supporting multi-device ISP flows. Note that newer Altera MAX V / MAX 10 CPLDs have superseded this part - the EPM9560 is generally used today for legacy design maintenance.

This page synthesizes distributor stock data, parametric drop-in alternatives, and practical design guidance not found in the original MAX 9000 datasheet.

Alternatives de remplacement direct pour EPM9560RC208-14 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPM9560RC208-14 (même facteur de forme et même empreinte) — différant par Package, Speed Grade, User I/O Pins, Propagation Delay (tPD), Usable Gates.

EPM9560ARC208-10

Intel

Package: 208-pin RQFP (PowerQuad Flat Pack) with exposed pad

User I/O Pins: 153 I/O

Propagation Delay (tPD): 10 ns (speed grade -10)