EPM9560RI240-20C - MAX 9000 560-Macrocell CPLD, 240-RQFP | Altera
Référence : EPM9560RI240-20C ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $78.5 | $78,50 |
| 10 | $71.2 | $712,00 |
| 100 | $64.8 | $6 480,00 |
| 500 | $58.4 | $29 200,00 |
| 1 000 | $52.1 | $52 100,00 |
EPM9560RI240-20C Présentation
What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that combines the instant-on, deterministic timing of traditional PAL/GAL devices with much higher logic density. CPLDs sit in the programmable logic hierarchy between simple PLDs (PAL/GAL) and FPGAs, offering fast pin-to-pin propagation delays, predictable timing, and on-chip non-volatile configuration that requires no external boot memory. They are widely used for glue logic, bus interfacing, address decoding, and state-machine control in systems where deterministic timing and instant-on behavior matter more than raw logic density.
Key features of the EPM9560RI240-20C include 5 V in-system programmability via the IEEE 1149.1 JTAG boundary-scan test (BST) interface, support for 3.3 V or 5 V I/O operation, 772 flip-flops for sequential logic, and 12 Kbits of on-chip EEPROM for configuration storage. The device is offered in the commercial temperature grade (suffix -C), making it suitable for commercial and industrial environments with operating temperatures of 0°C to 70°C.
Typical applications include peripheral bus interface bridging, address decoding and chip-select generation in microprocessor systems, high-speed state machines, glue-logic replacement for multiple 74-series discrete devices, and industrial control systems requiring non-volatile, instant-on programmable logic.
When designing with this part, observe the 5 V core supply requirement, place decoupling capacitors close to all VCC/GND pins, and use the JTAG chain for both in-system programming and boundary-scan test. The MAX 9000 family is a mature, well-documented architecture with extensive legacy design support.
Alternatives de remplacement direct pour EPM9560RI240-20C — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPM9560RI240-20C (même facteur de forme et même empreinte) — différant par Package, Programming Interface, Macrocells, Device Type, Process Technology.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPM9560RI240-20
✅ Remplacement direct✓ En stock
Contactez-nous pour le prix
Voir la fiche technique →EPM9560RI240-15C
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EPM9560RI240-10
✅ Remplacement direct✓ En stock
Contactez-nous pour le prix
Voir la fiche technique →EPM9480RC240-20
✅ Remplacement direct✓ En stock
$8.4 / unité
Voir la fiche technique →EPM9480RC240-20C
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EPM9560RI240-20C Valeurs maximales et caractéristiques électriques
| Family | MAX 9000 |
| Device Type | EE PLD (CPLD) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| User I/Os | 191 |
| Internal Operating Frequency | 100 MHz |
| Propagation Delay (tPD) | 20 ns (speed grade -20) |
| Supply Voltage (VCCINT) | 5 V |
| I/O Voltage | 3.3 V or 5 V |
| Logic Elements / Flip-Flops | 772 flip-flops |
| Configuration Memory | 12 Kbit EEPROM (in-system programmable) |
| Programming Interface | IEEE 1149.1 JTAG BST |
| Température de fonctionnement | 0°C to +70°C (commercial grade) |
| Boîtier | 240-pin RQFP (Power Quad Flat Pack) |
| Process Technology | CMOS, EEPROM-based |
Configuration des broches de EPM9560RI240-20C
| Broche 1 | I/O — User I/O pin (bank 1) |
| Broche 2 | I/O — User I/O pin (bank 1) |
| Broche 3 | I/O — User I/O pin (bank 1) |
| Broche 4 | I/O — User I/O pin (bank 1) |
| Broche 5 | GND — Ground |
| Broche 6 | I/O — User I/O pin (bank 1) |
| Broche 7 | I/O — User I/O pin (bank 1) |
| Broche 8 | I/O — User I/O pin (bank 1) |
| Broche 9 | I/O — User I/O pin (bank 1) |
| Broche 10 | VCC — 5 V core supply |
| Broche 11 | I/O — User I/O pin (bank 2) |
| Broche 12 | I/O — User I/O pin (bank 2) |
| Broche 13 | I/O — User I/O pin (bank 2) |
| Broche 14 | I/O — User I/O pin (bank 2) |
| Broche 15 | I/O — User I/O pin (bank 2) |
| Broche 16 | I/O — User I/O pin (bank 2) |
| Broche 17 | GND — Ground |
| Broche 18 | I/O — User I/O pin (bank 2) |
| Broche 19 | I/O — User I/O pin (bank 2) |
| Broche 20 | I/O — User I/O pin (bank 2) |
| Broche 21 | I/O — User I/O pin (bank 2) |
| Broche 22 | VCC — 5 V core supply |
| Broche 23 | I/O — User I/O pin (bank 3) |
| Broche 24 | I/O — User I/O pin (bank 3) |
| Broche 25 | I/O — User I/O pin (bank 3) |
| Broche 26 | I/O — User I/O pin (bank 3) |
| Broche 27 | I/O — User I/O pin (bank 3) |
| Broche 28 | GND — Ground |
| Broche 29 | I/O — User I/O pin (bank 3) |
| Broche 30 | I/O — User I/O pin (bank 3) |
| Broche 31 | I/O — User I/O pin (bank 3) |
| Broche 32 | I/O — User I/O pin (bank 3) |
| Broche 33 | I/O — User I/O pin (bank 3) |
| Broche 34 | VCC — 5 V core supply |
| Broche 35 | I/O — User I/O pin (bank 4) |
| Broche 36 | I/O — User I/O pin (bank 4) |
| Broche 37 | I/O — User I/O pin (bank 4) |
| Broche 38 | I/O — User I/O pin (bank 4) |
| Broche 39 | GND — Ground |
| Broche 40 | I/O — User I/O pin (bank 4) |
| Broche 41 | I/O — User I/O pin (bank 4) |
| Broche 42 | I/O — User I/O pin (bank 4) |
| Broche 43 | I/O — User I/O pin (bank 4) |
| Broche 44 | I/O — User I/O pin (bank 4) |
| Broche 45 | VCC — 5 V core supply |
| Broche 46 | I/O — User I/O pin (bank 5) |
| Broche 47 | I/O — User I/O pin (bank 5) |
| Broche 48 | I/O — User I/O pin (bank 5) |
| Broche 49 | I/O — User I/O pin (bank 5) |
| Broche 50 | GND — Ground |
| Broche 51 | I/O — User I/O pin (bank 5) |
| Broche 52 | I/O — User I/O pin (bank 5) |
| Broche 53 | I/O — User I/O pin (bank 5) |
| Broche 54 | I/O — User I/O pin (bank 5) |
| Broche 55 | I/O — User I/O pin (bank 5) |
| Broche 56 | VCC — 5 V core supply |
| Broche 57 | I/O — User I/O pin (bank 6) |
| Broche 58 | I/O — User I/O pin (bank 6) |
| Broche 59 | I/O — User I/O pin (bank 6) |
| Broche 60 | I/O — User I/O pin (bank 6) |
| Broche 61 | GND — Ground |
| Broche 62 | I/O — User I/O pin (bank 6) |
| Broche 63 | I/O — User I/O pin (bank 6) |
| Broche 64 | I/O — User I/O pin (bank 6) |
| Broche 65 | I/O — User I/O pin (bank 6) |
| Broche 66 | I/O — User I/O pin (bank 6) |
| Broche 67 | VCC — 5 V core supply |
| Broche 68 | I/O — User I/O pin (bank 7) |
| Broche 69 | I/O — User I/O pin (bank 7) |
| Broche 70 | I/O — User I/O pin (bank 7) |
| Broche 71 | I/O — User I/O pin (bank 7) |
| Broche 72 | GND — Ground |
| Broche 73 | I/O — User I/O pin (bank 7) |
| Broche 74 | I/O — User I/O pin (bank 7) |
| Broche 75 | I/O — User I/O pin (bank 7) |
| Broche 76 | I/O — User I/O pin (bank 7) |
| Broche 77 | I/O — User I/O pin (bank 7) |
| Broche 78 | VCC — 5 V core supply |
| Broche 79 | I/O — User I/O pin (bank 8) |
| Broche 80 | I/O — User I/O pin (bank 8) |
| Broche 81 | I/O — User I/O pin (bank 8) |
| Broche 82 | I/O — User I/O pin (bank 8) |
| Broche 83 | GND — Ground |
| Broche 84 | I/O — User I/O pin (bank 8) |
| Broche 85 | I/O — User I/O pin (bank 8) |
| Broche 86 | I/O — User I/O pin (bank 8) |
| Broche 87 | I/O — User I/O pin (bank 8) |
| Broche 88 | I/O — User I/O pin (bank 8) |
| Broche 89 | VCC — 5 V core supply |
| Broche 90 | I/O — User I/O pin (bank 9) |
| Broche 91 | I/O — User I/O pin (bank 9) |
| Broche 92 | I/O — User I/O pin (bank 9) |
| Broche 93 | I/O — User I/O pin (bank 9) |
| Broche 94 | GND — Ground |
| Broche 95 | I/O — User I/O pin (bank 9) |
| Broche 96 | I/O — User I/O pin (bank 9) |
| Broche 97 | I/O — User I/O pin (bank 9) |
| Broche 98 | I/O — User I/O pin (bank 9) |
| Broche 99 | I/O — User I/O pin (bank 9) |
| Broche 100 | VCC — 5 V core supply |
| Broche 101 | I/O — User I/O pin (bank 10) |
| Broche 102 | I/O — User I/O pin (bank 10) |
| Broche 103 | I/O — User I/O pin (bank 10) |
| Broche 104 | I/O — User I/O pin (bank 10) |
| Broche 105 | GND — Ground |
| Broche 106 | I/O — User I/O pin (bank 10) |
| Broche 107 | I/O — User I/O pin (bank 10) |
| Broche 108 | I/O — User I/O pin (bank 10) |
| Broche 109 | I/O — User I/O pin (bank 10) |
| Broche 110 | I/O — User I/O pin (bank 10) |
| Broche 111 | VCC — 5 V core supply |
| Broche 112 | I/O — User I/O pin (bank 11) |
| Broche 113 | I/O — User I/O pin (bank 11) |
| Broche 114 | I/O — User I/O pin (bank 11) |
| Broche 115 | I/O — User I/O pin (bank 11) |
| Broche 116 | GND — Ground |
| Broche 117 | I/O — User I/O pin (bank 11) |
| Broche 118 | I/O — User I/O pin (bank 11) |
| Broche 119 | I/O — User I/O pin (bank 11) |
| Broche 120 | I/O — User I/O pin (bank 11) |
| Broche 121 | I/O — User I/O pin (bank 11) |
| Broche 122 | VCC — 5 V core supply |
| Broche 123 | I/O — User I/O pin (bank 12) |
| Broche 124 | I/O — User I/O pin (bank 12) |
| Broche 125 | I/O — User I/O pin (bank 12) |
| Broche 126 | I/O — User I/O pin (bank 12) |
| Broche 127 | GND — Ground |
| Broche 128 | I/O — User I/O pin (bank 12) |
| Broche 129 | I/O — User I/O pin (bank 12) |
| Broche 130 | I/O — User I/O pin (bank 12) |
| Broche 131 | I/O — User I/O pin (bank 12) |
| Broche 132 | I/O — User I/O pin (bank 12) |
| Broche 133 | VCC — 5 V core supply |
| Broche 134 | I/O — User I/O pin (bank 13) |
| Broche 135 | I/O — User I/O pin (bank 13) |
| Broche 136 | I/O — User I/O pin (bank 13) |
| Broche 137 | I/O — User I/O pin (bank 13) |
| Broche 138 | GND — Ground |
| Broche 139 | I/O — User I/O pin (bank 13) |
| Broche 140 | I/O — User I/O pin (bank 13) |
| Broche 141 | I/O — User I/O pin (bank 13) |
| Broche 142 | I/O — User I/O pin (bank 13) |
| Broche 143 | I/O — User I/O pin (bank 13) |
| Broche 144 | VCC — 5 V core supply |
| Broche 145 | I/O — User I/O pin (bank 14) |
| Broche 146 | I/O — User I/O pin (bank 14) |
| Broche 147 | I/O — User I/O pin (bank 14) |
| Broche 148 | I/O — User I/O pin (bank 14) |
| Broche 149 | GND — Ground |
| Broche 150 | I/O — User I/O pin (bank 14) |
| Broche 151 | I/O — User I/O pin (bank 14) |
| Broche 152 | I/O — User I/O pin (bank 14) |
| Broche 153 | I/O — User I/O pin (bank 14) |
| Broche 154 | I/O — User I/O pin (bank 14) |
| Broche 155 | VCC — 5 V core supply |
| Broche 156 | I/O — User I/O pin (bank 15) |
| Broche 157 | I/O — User I/O pin (bank 15) |
| Broche 158 | I/O — User I/O pin (bank 15) |
| Broche 159 | I/O — User I/O pin (bank 15) |
| Broche 160 | GND — Ground |
| Broche 161 | I/O — User I/O pin (bank 15) |
| Broche 162 | I/O — User I/O pin (bank 15) |
| Broche 163 | I/O — User I/O pin (bank 15) |
| Broche 164 | I/O — User I/O pin (bank 15) |
| Broche 165 | I/O — User I/O pin (bank 15) |
| Broche 166 | VCC — 5 V core supply |
| Broche 167 | I/O — User I/O pin (bank 16) |
| Broche 168 | I/O — User I/O pin (bank 16) |
| Broche 169 | I/O — User I/O pin (bank 16) |
| Broche 170 | I/O — User I/O pin (bank 16) |
| Broche 171 | GND — Ground |
| Broche 172 | I/O — User I/O pin (bank 16) |
| Broche 173 | I/O — User I/O pin (bank 16) |
| Broche 174 | I/O — User I/O pin (bank 16) |
| Broche 175 | I/O — User I/O pin (bank 16) |
| Broche 176 | I/O — User I/O pin (bank 16) |
| Broche 177 | VCC — 5 V core supply |
| Broche 178 | I/O — User I/O pin (bank 17) |
| Broche 179 | I/O — User I/O pin (bank 17) |
| Broche 180 | I/O — User I/O pin (bank 17) |
| Broche 181 | I/O — User I/O pin (bank 17) |
| Broche 182 | GND — Ground |
| Broche 183 | I/O — User I/O pin (bank 17) |
| Broche 184 | I/O — User I/O pin (bank 17) |
| Broche 185 | I/O — User I/O pin (bank 17) |
| Broche 186 | I/O — User I/O pin (bank 17) |
| Broche 187 | I/O — User I/O pin (bank 17) |
| Broche 188 | VCC — 5 V core supply |
| Broche 189 | I/O — User I/O pin (bank 18) |
| Broche 190 | I/O — User I/O pin (bank 18) |
| Broche 191 | I/O — User I/O pin (bank 18) |
| Broche 192 | I/O — User I/O pin (bank 18) |
| Broche 193 | GND — Ground |
| Broche 194 | I/O — User I/O pin (bank 18) |
| Broche 195 | I/O — User I/O pin (bank 18) |
| Broche 196 | I/O — User I/O pin (bank 18) |
| Broche 197 | I/O — User I/O pin (bank 18) |
| Broche 198 | I/O — User I/O pin (bank 18) |
| Broche 199 | VCC — 5 V core supply |
| Broche 200 | I/O — User I/O pin (bank 19) |
| Broche 201 | I/O — User I/O pin (bank 19) |
| Broche 202 | I/O — User I/O pin (bank 19) |
| Broche 203 | I/O — User I/O pin (bank 19) |
| Broche 204 | GND — Ground |
| Broche 205 | I/O — User I/O pin (bank 19) |
| Broche 206 | I/O — User I/O pin (bank 19) |
| Broche 207 | I/O — User I/O pin (bank 19) |
| Broche 208 | I/O — User I/O pin (bank 19) |
| Broche 209 | I/O — User I/O pin (bank 19) |
| Broche 210 | VCC — 5 V core supply |
| Broche 211 | I/O — User I/O pin (bank 20) |
| Broche 212 | I/O — User I/O pin (bank 20) |
| Broche 213 | I/O — User I/O pin (bank 20) |
| Broche 214 | I/O — User I/O pin (bank 20) |
| Broche 215 | GND — Ground |
| Broche 216 | I/O — User I/O pin (bank 20) |
| Broche 217 | I/O — User I/O pin (bank 20) |
| Broche 218 | I/O — User I/O pin (bank 20) |
| Broche 219 | I/O — User I/O pin (bank 20) |
| Broche 220 | I/O — User I/O pin (bank 20) |
| Broche 221 | VCC — 5 V core supply |
| Broche 222 | I/O — User I/O pin (bank 21) |
| Broche 223 | I/O — User I/O pin (bank 21) |
| Broche 224 | I/O — User I/O pin (bank 21) |
| Broche 225 | I/O — User I/O pin (bank 21) |
| Broche 226 | GND — Ground |
| Broche 227 | I/O — User I/O pin (bank 21) |
| Broche 228 | I/O — User I/O pin (bank 21) |
| Broche 229 | I/O — User I/O pin (bank 21) |
| Broche 230 | I/O — User I/O pin (bank 21) |
| Broche 231 | I/O — User I/O pin (bank 21) |
| Broche 232 | VCC — 5 V core supply |
| Broche 233 | I/O — User I/O pin (bank 22) |
| Broche 234 | I/O — User I/O pin (bank 22) |
| Broche 235 | I/O — User I/O pin (bank 22) |
| Broche 236 | I/O — User I/O pin (bank 22) |
| Broche 237 | GND — Ground |
| Broche 238 | I/O — User I/O pin (bank 22) |
| Broche 239 | TDI — JTAG Test Data Input |
| Broche 240 | TMS — JTAG Test Mode Select |
Applications typiques
EPM9560RI240-20C convient pour 6 applications: Microprocessor Glue Logic, Peripheral Bus Interface Bridging, Address Decoding and Chip Select Generation, High-Speed State Machine Controllers, Industrial Control and Instrumentation, Legacy System Modernization.
Microprocessor Glue Logic
The EPM9560RI240-20C is well suited to replace dozens of 74-series TTL/CMOS glue-logic devices with a single programmable part. Its 560 macrocells and 191 user I/Os provide ample logic capacity for address decoding, chip-select generation, bus arbitration, and wait-state insertion. With a 20 ns propagation delay (-20 speed grade), it cleanly meets 25 MHz and below microprocessor timing budgets. The 5 V core and 3.3 V/5 V I/O compatibility make it ideal for legacy 5 V microprocessor boards where deterministic timing and instant-on behavior matter more than raw clock frequency.
Recommandé
Peripheral Bus Interface Bridging
The EPM9560RI240-20C excels at bridging mismatched peripheral buses - such as ISA-to-PCI, microcontroller-to-DSP, or asynchronous-to-synchronous protocol conversion. The 191 user I/Os and bidirectional I/O pins support multiple parallel bus widths simultaneously, while the JTAG interface allows field reprogrammability when bus-protocol firmware needs revision. Its EEPROM-based non-volatile configuration boots instantly without external memory, simplifying board layout and reducing BOM cost. The 5 V tolerant I/Os interface cleanly with legacy 5 V peripherals.
Recommandé
Address Decoding and Chip Select Generation
For microprocessor systems with large memory maps, the EPM9560RI240-20C's 560 macrocells and 191 I/Os handle complex address decoding and chip-select generation across wide address buses. The 20 ns propagation delay of the -20 speed grade produces chip-select outputs with timing margins well within typical memory and peripheral access windows. Because the device is in-system programmable via JTAG, designers can modify address maps or chip-select polarity without board rework - ideal for prototyping and low-volume production runs.
Recommandé
High-Speed State Machine Controllers
The EPM9560RI240-20C implements complex Moore or Mealy state machines in deterministic, parallel hardware that runs up to 100 MHz internally. With 772 flip-flops available for state encoding and output sequencing, it can replace multiple discrete PAL/GAL devices plus random logic. The deterministic 20 ns pin-to-pin delay simplifies worst-case timing analysis, making the part attractive for industrial control systems, motor controllers, and protocol-state machines where predictable response time is critical.
Recommandé
Industrial Control and Instrumentation
In industrial control cabinets, the EPM9560RI240-20C delivers reliable glue logic and protocol conversion with the instant-on behavior required for deterministic system startup. Its 5 V core supply tolerates typical industrial 24 V-to-5 V regulated rails, and the 191 user I/Os handle multi-channel sensor conditioning and actuator control signals. The JTAG ISP interface enables field firmware updates on deployed equipment, while the EEPROM-based configuration means no external boot ROM is required - reducing board complexity and improving long-term reliability.
Recommandé
Legacy System Modernization
The EPM9560RI240-20C is widely used to modernize legacy 5 V systems by consolidating dozens of discrete 74F/74LS/74HC logic devices into a single programmable part. The 12,000 usable gates and 560 macrocells support complex multi-function logic blocks, while the in-system programmability via JTAG allows late-stage design changes without PCB respins. Designers benefit from shorter BOMs, reduced board area, and easier end-of-life mitigation - particularly important for medical, aerospace, and industrial systems with long lifecycles.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPM9560RI240-20C — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPM9560RI240-20 | EPM9560RI240-15C | EPM9560RI240-10 | EPM9480RC240-20 | EPM9480RC240-20C |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 240-pin RQFP | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same |
| Macrocells | 560 | 560 | 560 | 560 | 480 | 480 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 10,000 | 10,000 |
| Propagation Delay (tPD) | 20 ns (-20 grade) | 20 ns (-20) | 15 ns (-15 grade) | 10 ns (-10 grade) | 20 ns (-20) | 20 ns (-20) |
| User I/Os | 191 | 191 | 191 | 191 | 191 | 191 |
| Operating Temperature | 0 to +70 °C (commercial) | Industrial / wider | 0 to +70 °C (commercial) | Industrial / wider | Industrial / wider | 0 to +70 °C (commercial) |
Principaux différenciateurs
- Highest density in the MAX 9000 family (vs EPM9480RC240-20C)
- Commercial temperature grade at lower cost (vs EPM9560RI240-20)
- Standard -20 speed grade balances cost and timing margin (vs EPM9560RI240-10)
Notes de conception
The EPM9560RI240-20C requires a stable 5 V VCCINT supply with adequate decoupling. Place one 0.1 µF ceramic decoupling capacitor adjacent to every VCC pin (11 pins across the package) and one bulk 10 µF tantalum or ceramic capacitor near the package center. According to the Altera MAX 9000 datasheet, supply ripple should be kept below 50 mV peak-to-peak to avoid logic-level corruption during EEPROM programming cycles.
Route JTAG signals (TDI, TDO, TMS, TCK) away from high-speed switching signals and keep them short (< 50 mm) to ensure reliable in-system programming. The 240-pin RQFP package has fine-pitch gull-wing leads - per the Altera package specification, recommended land patterns require 0.5 mm lead pitch with 0.3 mm stencil apertures for reflow. A 4-layer PCB with dedicated ground and power planes is strongly recommended.
Do not exceed the 5 V VCCINT maximum - the EPM9560RI240-20C is NOT a 3.3 V core device, only its I/O banks can be 3.3 V. Ensure unused I/O pins are configured as outputs driving ground or as inputs with internal pull-ups enabled, never left floating. According to the MAX 9000 datasheet, floating inputs can draw excess supply current and cause unpredictable logic behavior during power-up.
Informations de conformité
EPM9560RI240-20C is a legacy Altera (now Intel) MAX 9000 CPLD in NRD status. Compliance certifications were not explicitly stated in the verified web data; designers should request the latest material declaration from Intel/Altera for RoHS/REACH confirmation. Not qualified to AEC-Q100 (commercial temperature grade only).
