EPM9560RI240-20C - MAX 9000 560-Macrocell CPLD, 240-RQFP | Altera
MPN: EPM9560RI240-20C β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $71.2 | $712.00 |
| 100 | $64.8 | $6,480.00 |
| 500 | $58.4 | $29,200.00 |
| 1,000 | $52.1 | $52,100.00 |
Drop-in alternatives for EPM9560RI240-20C β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RI240-20
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPM9560RI240-15C
β Drop-Inπ Reference alternative (not in catalog)
EPM9560RI240-10
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPM9480RC240-20
β Drop-Inβ In Stock
$8.4 / Unit
View Datasheet βEPM9480RC240-20C
β Drop-Inπ Reference alternative (not in catalog)
EPM9560RI240-20C Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | EE PLD (CPLD) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| User I/Os | 191 |
| Internal Operating Frequency | 100 MHz |
| Propagation Delay (tPD) | 20 ns (speed grade -20) |
| Supply Voltage (VCCINT) | 5 V |
| I/O Voltage | 3.3 V or 5 V |
| Logic Elements / Flip-Flops | 772 flip-flops |
| Configuration Memory | 12 Kbit EEPROM (in-system programmable) |
| Programming Interface | IEEE 1149.1 JTAG BST |
| Operating Temperature | 0Β°C to +70Β°C (commercial grade) |
| Package | 240-pin RQFP (Power Quad Flat Pack) |
| Process Technology | CMOS, EEPROM-based |
EPM9560RI240-20C Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | GND β Ground |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | VCC β 5 V core supply |
| Pin 11 | I/O β User I/O pin (bank 2) |
| Pin 12 | I/O β User I/O pin (bank 2) |
| Pin 13 | I/O β User I/O pin (bank 2) |
| Pin 14 | I/O β User I/O pin (bank 2) |
| Pin 15 | I/O β User I/O pin (bank 2) |
| Pin 16 | I/O β User I/O pin (bank 2) |
| Pin 17 | GND β Ground |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | I/O β User I/O pin (bank 2) |
| Pin 22 | VCC β 5 V core supply |
| Pin 23 | I/O β User I/O pin (bank 3) |
| Pin 24 | I/O β User I/O pin (bank 3) |
| Pin 25 | I/O β User I/O pin (bank 3) |
| Pin 26 | I/O β User I/O pin (bank 3) |
| Pin 27 | I/O β User I/O pin (bank 3) |
| Pin 28 | GND β Ground |
| Pin 29 | I/O β User I/O pin (bank 3) |
| Pin 30 | I/O β User I/O pin (bank 3) |
| Pin 31 | I/O β User I/O pin (bank 3) |
| Pin 32 | I/O β User I/O pin (bank 3) |
| Pin 33 | I/O β User I/O pin (bank 3) |
| Pin 34 | VCC β 5 V core supply |
| Pin 35 | I/O β User I/O pin (bank 4) |
| Pin 36 | I/O β User I/O pin (bank 4) |
| Pin 37 | I/O β User I/O pin (bank 4) |
| Pin 38 | I/O β User I/O pin (bank 4) |
| Pin 39 | GND β Ground |
| Pin 40 | I/O β User I/O pin (bank 4) |
| Pin 41 | I/O β User I/O pin (bank 4) |
| Pin 42 | I/O β User I/O pin (bank 4) |
| Pin 43 | I/O β User I/O pin (bank 4) |
| Pin 44 | I/O β User I/O pin (bank 4) |
| Pin 45 | VCC β 5 V core supply |
| Pin 46 | I/O β User I/O pin (bank 5) |
| Pin 47 | I/O β User I/O pin (bank 5) |
| Pin 48 | I/O β User I/O pin (bank 5) |
| Pin 49 | I/O β User I/O pin (bank 5) |
| Pin 50 | GND β Ground |
| Pin 51 | I/O β User I/O pin (bank 5) |
| Pin 52 | I/O β User I/O pin (bank 5) |
| Pin 53 | I/O β User I/O pin (bank 5) |
| Pin 54 | I/O β User I/O pin (bank 5) |
| Pin 55 | I/O β User I/O pin (bank 5) |
| Pin 56 | VCC β 5 V core supply |
| Pin 57 | I/O β User I/O pin (bank 6) |
| Pin 58 | I/O β User I/O pin (bank 6) |
| Pin 59 | I/O β User I/O pin (bank 6) |
| Pin 60 | I/O β User I/O pin (bank 6) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin (bank 6) |
| Pin 63 | I/O β User I/O pin (bank 6) |
| Pin 64 | I/O β User I/O pin (bank 6) |
| Pin 65 | I/O β User I/O pin (bank 6) |
| Pin 66 | I/O β User I/O pin (bank 6) |
| Pin 67 | VCC β 5 V core supply |
| Pin 68 | I/O β User I/O pin (bank 7) |
| Pin 69 | I/O β User I/O pin (bank 7) |
| Pin 70 | I/O β User I/O pin (bank 7) |
| Pin 71 | I/O β User I/O pin (bank 7) |
| Pin 72 | GND β Ground |
| Pin 73 | I/O β User I/O pin (bank 7) |
| Pin 74 | I/O β User I/O pin (bank 7) |
| Pin 75 | I/O β User I/O pin (bank 7) |
| Pin 76 | I/O β User I/O pin (bank 7) |
| Pin 77 | I/O β User I/O pin (bank 7) |
| Pin 78 | VCC β 5 V core supply |
| Pin 79 | I/O β User I/O pin (bank 8) |
| Pin 80 | I/O β User I/O pin (bank 8) |
| Pin 81 | I/O β User I/O pin (bank 8) |
| Pin 82 | I/O β User I/O pin (bank 8) |
| Pin 83 | GND β Ground |
| Pin 84 | I/O β User I/O pin (bank 8) |
| Pin 85 | I/O β User I/O pin (bank 8) |
| Pin 86 | I/O β User I/O pin (bank 8) |
| Pin 87 | I/O β User I/O pin (bank 8) |
| Pin 88 | I/O β User I/O pin (bank 8) |
| Pin 89 | VCC β 5 V core supply |
| Pin 90 | I/O β User I/O pin (bank 9) |
| Pin 91 | I/O β User I/O pin (bank 9) |
| Pin 92 | I/O β User I/O pin (bank 9) |
| Pin 93 | I/O β User I/O pin (bank 9) |
| Pin 94 | GND β Ground |
| Pin 95 | I/O β User I/O pin (bank 9) |
| Pin 96 | I/O β User I/O pin (bank 9) |
| Pin 97 | I/O β User I/O pin (bank 9) |
| Pin 98 | I/O β User I/O pin (bank 9) |
| Pin 99 | I/O β User I/O pin (bank 9) |
| Pin 100 | VCC β 5 V core supply |
| Pin 101 | I/O β User I/O pin (bank 10) |
| Pin 102 | I/O β User I/O pin (bank 10) |
| Pin 103 | I/O β User I/O pin (bank 10) |
| Pin 104 | I/O β User I/O pin (bank 10) |
| Pin 105 | GND β Ground |
| Pin 106 | I/O β User I/O pin (bank 10) |
| Pin 107 | I/O β User I/O pin (bank 10) |
| Pin 108 | I/O β User I/O pin (bank 10) |
| Pin 109 | I/O β User I/O pin (bank 10) |
| Pin 110 | I/O β User I/O pin (bank 10) |
| Pin 111 | VCC β 5 V core supply |
| Pin 112 | I/O β User I/O pin (bank 11) |
| Pin 113 | I/O β User I/O pin (bank 11) |
| Pin 114 | I/O β User I/O pin (bank 11) |
| Pin 115 | I/O β User I/O pin (bank 11) |
| Pin 116 | GND β Ground |
| Pin 117 | I/O β User I/O pin (bank 11) |
| Pin 118 | I/O β User I/O pin (bank 11) |
| Pin 119 | I/O β User I/O pin (bank 11) |
| Pin 120 | I/O β User I/O pin (bank 11) |
| Pin 121 | I/O β User I/O pin (bank 11) |
| Pin 122 | VCC β 5 V core supply |
| Pin 123 | I/O β User I/O pin (bank 12) |
| Pin 124 | I/O β User I/O pin (bank 12) |
| Pin 125 | I/O β User I/O pin (bank 12) |
| Pin 126 | I/O β User I/O pin (bank 12) |
| Pin 127 | GND β Ground |
| Pin 128 | I/O β User I/O pin (bank 12) |
| Pin 129 | I/O β User I/O pin (bank 12) |
| Pin 130 | I/O β User I/O pin (bank 12) |
| Pin 131 | I/O β User I/O pin (bank 12) |
| Pin 132 | I/O β User I/O pin (bank 12) |
| Pin 133 | VCC β 5 V core supply |
| Pin 134 | I/O β User I/O pin (bank 13) |
| Pin 135 | I/O β User I/O pin (bank 13) |
| Pin 136 | I/O β User I/O pin (bank 13) |
| Pin 137 | I/O β User I/O pin (bank 13) |
| Pin 138 | GND β Ground |
| Pin 139 | I/O β User I/O pin (bank 13) |
| Pin 140 | I/O β User I/O pin (bank 13) |
| Pin 141 | I/O β User I/O pin (bank 13) |
| Pin 142 | I/O β User I/O pin (bank 13) |
| Pin 143 | I/O β User I/O pin (bank 13) |
| Pin 144 | VCC β 5 V core supply |
| Pin 145 | I/O β User I/O pin (bank 14) |
| Pin 146 | I/O β User I/O pin (bank 14) |
| Pin 147 | I/O β User I/O pin (bank 14) |
| Pin 148 | I/O β User I/O pin (bank 14) |
| Pin 149 | GND β Ground |
| Pin 150 | I/O β User I/O pin (bank 14) |
| Pin 151 | I/O β User I/O pin (bank 14) |
| Pin 152 | I/O β User I/O pin (bank 14) |
| Pin 153 | I/O β User I/O pin (bank 14) |
| Pin 154 | I/O β User I/O pin (bank 14) |
| Pin 155 | VCC β 5 V core supply |
| Pin 156 | I/O β User I/O pin (bank 15) |
| Pin 157 | I/O β User I/O pin (bank 15) |
| Pin 158 | I/O β User I/O pin (bank 15) |
| Pin 159 | I/O β User I/O pin (bank 15) |
| Pin 160 | GND β Ground |
| Pin 161 | I/O β User I/O pin (bank 15) |
| Pin 162 | I/O β User I/O pin (bank 15) |
| Pin 163 | I/O β User I/O pin (bank 15) |
| Pin 164 | I/O β User I/O pin (bank 15) |
| Pin 165 | I/O β User I/O pin (bank 15) |
| Pin 166 | VCC β 5 V core supply |
| Pin 167 | I/O β User I/O pin (bank 16) |
| Pin 168 | I/O β User I/O pin (bank 16) |
| Pin 169 | I/O β User I/O pin (bank 16) |
| Pin 170 | I/O β User I/O pin (bank 16) |
| Pin 171 | GND β Ground |
| Pin 172 | I/O β User I/O pin (bank 16) |
| Pin 173 | I/O β User I/O pin (bank 16) |
| Pin 174 | I/O β User I/O pin (bank 16) |
| Pin 175 | I/O β User I/O pin (bank 16) |
| Pin 176 | I/O β User I/O pin (bank 16) |
| Pin 177 | VCC β 5 V core supply |
| Pin 178 | I/O β User I/O pin (bank 17) |
| Pin 179 | I/O β User I/O pin (bank 17) |
| Pin 180 | I/O β User I/O pin (bank 17) |
| Pin 181 | I/O β User I/O pin (bank 17) |
| Pin 182 | GND β Ground |
| Pin 183 | I/O β User I/O pin (bank 17) |
| Pin 184 | I/O β User I/O pin (bank 17) |
| Pin 185 | I/O β User I/O pin (bank 17) |
| Pin 186 | I/O β User I/O pin (bank 17) |
| Pin 187 | I/O β User I/O pin (bank 17) |
| Pin 188 | VCC β 5 V core supply |
| Pin 189 | I/O β User I/O pin (bank 18) |
| Pin 190 | I/O β User I/O pin (bank 18) |
| Pin 191 | I/O β User I/O pin (bank 18) |
| Pin 192 | I/O β User I/O pin (bank 18) |
| Pin 193 | GND β Ground |
| Pin 194 | I/O β User I/O pin (bank 18) |
| Pin 195 | I/O β User I/O pin (bank 18) |
| Pin 196 | I/O β User I/O pin (bank 18) |
| Pin 197 | I/O β User I/O pin (bank 18) |
| Pin 198 | I/O β User I/O pin (bank 18) |
| Pin 199 | VCC β 5 V core supply |
| Pin 200 | I/O β User I/O pin (bank 19) |
| Pin 201 | I/O β User I/O pin (bank 19) |
| Pin 202 | I/O β User I/O pin (bank 19) |
| Pin 203 | I/O β User I/O pin (bank 19) |
| Pin 204 | GND β Ground |
| Pin 205 | I/O β User I/O pin (bank 19) |
| Pin 206 | I/O β User I/O pin (bank 19) |
| Pin 207 | I/O β User I/O pin (bank 19) |
| Pin 208 | I/O β User I/O pin (bank 19) |
| Pin 209 | I/O β User I/O pin (bank 19) |
| Pin 210 | VCC β 5 V core supply |
| Pin 211 | I/O β User I/O pin (bank 20) |
| Pin 212 | I/O β User I/O pin (bank 20) |
| Pin 213 | I/O β User I/O pin (bank 20) |
| Pin 214 | I/O β User I/O pin (bank 20) |
| Pin 215 | GND β Ground |
| Pin 216 | I/O β User I/O pin (bank 20) |
| Pin 217 | I/O β User I/O pin (bank 20) |
| Pin 218 | I/O β User I/O pin (bank 20) |
| Pin 219 | I/O β User I/O pin (bank 20) |
| Pin 220 | I/O β User I/O pin (bank 20) |
| Pin 221 | VCC β 5 V core supply |
| Pin 222 | I/O β User I/O pin (bank 21) |
| Pin 223 | I/O β User I/O pin (bank 21) |
| Pin 224 | I/O β User I/O pin (bank 21) |
| Pin 225 | I/O β User I/O pin (bank 21) |
| Pin 226 | GND β Ground |
| Pin 227 | I/O β User I/O pin (bank 21) |
| Pin 228 | I/O β User I/O pin (bank 21) |
| Pin 229 | I/O β User I/O pin (bank 21) |
| Pin 230 | I/O β User I/O pin (bank 21) |
| Pin 231 | I/O β User I/O pin (bank 21) |
| Pin 232 | VCC β 5 V core supply |
| Pin 233 | I/O β User I/O pin (bank 22) |
| Pin 234 | I/O β User I/O pin (bank 22) |
| Pin 235 | I/O β User I/O pin (bank 22) |
| Pin 236 | I/O β User I/O pin (bank 22) |
| Pin 237 | GND β Ground |
| Pin 238 | I/O β User I/O pin (bank 22) |
| Pin 239 | TDI β JTAG Test Data Input |
| Pin 240 | TMS β JTAG Test Mode Select |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RI240-20C is suitable for 6 applications: Microprocessor Glue Logic, Peripheral Bus Interface Bridging, Address Decoding and Chip Select Generation, High-Speed State Machine Controllers, Industrial Control and Instrumentation, Legacy System Modernization.
Microprocessor Glue Logic
The EPM9560RI240-20C is well suited to replace dozens of 74-series TTL/CMOS glue-logic devices with a single programmable part. Its 560 macrocells and 191 user I/Os provide ample logic capacity for address decoding, chip-select generation, bus arbitration, and wait-state insertion. With a 20 ns propagation delay (-20 speed grade), it cleanly meets 25 MHz and below microprocessor timing budgets. The 5 V core and 3.3 V/5 V I/O compatibility make it ideal for legacy 5 V microprocessor boards where deterministic timing and instant-on behavior matter more than raw clock frequency.
Recommended
Peripheral Bus Interface Bridging
The EPM9560RI240-20C excels at bridging mismatched peripheral buses - such as ISA-to-PCI, microcontroller-to-DSP, or asynchronous-to-synchronous protocol conversion. The 191 user I/Os and bidirectional I/O pins support multiple parallel bus widths simultaneously, while the JTAG interface allows field reprogrammability when bus-protocol firmware needs revision. Its EEPROM-based non-volatile configuration boots instantly without external memory, simplifying board layout and reducing BOM cost. The 5 V tolerant I/Os interface cleanly with legacy 5 V peripherals.
Recommended
Address Decoding and Chip Select Generation
For microprocessor systems with large memory maps, the EPM9560RI240-20C's 560 macrocells and 191 I/Os handle complex address decoding and chip-select generation across wide address buses. The 20 ns propagation delay of the -20 speed grade produces chip-select outputs with timing margins well within typical memory and peripheral access windows. Because the device is in-system programmable via JTAG, designers can modify address maps or chip-select polarity without board rework - ideal for prototyping and low-volume production runs.
Recommended
High-Speed State Machine Controllers
The EPM9560RI240-20C implements complex Moore or Mealy state machines in deterministic, parallel hardware that runs up to 100 MHz internally. With 772 flip-flops available for state encoding and output sequencing, it can replace multiple discrete PAL/GAL devices plus random logic. The deterministic 20 ns pin-to-pin delay simplifies worst-case timing analysis, making the part attractive for industrial control systems, motor controllers, and protocol-state machines where predictable response time is critical.
Recommended
Industrial Control and Instrumentation
In industrial control cabinets, the EPM9560RI240-20C delivers reliable glue logic and protocol conversion with the instant-on behavior required for deterministic system startup. Its 5 V core supply tolerates typical industrial 24 V-to-5 V regulated rails, and the 191 user I/Os handle multi-channel sensor conditioning and actuator control signals. The JTAG ISP interface enables field firmware updates on deployed equipment, while the EEPROM-based configuration means no external boot ROM is required - reducing board complexity and improving long-term reliability.
Recommended
Legacy System Modernization
The EPM9560RI240-20C is widely used to modernize legacy 5 V systems by consolidating dozens of discrete 74F/74LS/74HC logic devices into a single programmable part. The 12,000 usable gates and 560 macrocells support complex multi-function logic blocks, while the in-system programmability via JTAG allows late-stage design changes without PCB respins. Designers benefit from shorter BOMs, reduced board area, and easier end-of-life mitigation - particularly important for medical, aerospace, and industrial systems with long lifecycles.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RI240-20C β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RI240-20 | EPM9560RI240-15C | EPM9560RI240-10 | EPM9480RC240-20 | EPM9480RC240-20C |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 240-pin RQFP | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same |
| Macrocells | 560 | 560 | 560 | 560 | 480 | 480 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 10,000 | 10,000 |
| Propagation Delay (tPD) | 20 ns (-20 grade) | 20 ns (-20) | 15 ns (-15 grade) | 10 ns (-10 grade) | 20 ns (-20) | 20 ns (-20) |
| Internal Frequency | 100 MHz | 100 MHz | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| User I/Os | 191 | 191 | 191 | 191 | 191 | 191 |
| Operating Temperature | 0 to +70 Β°C (commercial) | Industrial / wider | 0 to +70 Β°C (commercial) | Industrial / wider | Industrial / wider | 0 to +70 Β°C (commercial) |
Key Differentiators
- Highest density in the MAX 9000 family (vs EPM9480RC240-20C)
- Commercial temperature grade at lower cost (vs EPM9560RI240-20)
- Standard -20 speed grade balances cost and timing margin (vs EPM9560RI240-10)
Design Notes
The EPM9560RI240-20C requires a stable 5 V VCCINT supply with adequate decoupling. Place one 0.1 Β΅F ceramic decoupling capacitor adjacent to every VCC pin (11 pins across the package) and one bulk 10 Β΅F tantalum or ceramic capacitor near the package center. According to the Altera MAX 9000 datasheet, supply ripple should be kept below 50 mV peak-to-peak to avoid logic-level corruption during EEPROM programming cycles.
Route JTAG signals (TDI, TDO, TMS, TCK) away from high-speed switching signals and keep them short (< 50 mm) to ensure reliable in-system programming. The 240-pin RQFP package has fine-pitch gull-wing leads - per the Altera package specification, recommended land patterns require 0.5 mm lead pitch with 0.3 mm stencil apertures for reflow. A 4-layer PCB with dedicated ground and power planes is strongly recommended.
Do not exceed the 5 V VCCINT maximum - the EPM9560RI240-20C is NOT a 3.3 V core device, only its I/O banks can be 3.3 V. Ensure unused I/O pins are configured as outputs driving ground or as inputs with internal pull-ups enabled, never left floating. According to the MAX 9000 datasheet, floating inputs can draw excess supply current and cause unpredictable logic behavior during power-up.
Compliance Information
EPM9560RI240-20C is a legacy Altera (now Intel) MAX 9000 CPLD in NRD status. Compliance certifications were not explicitly stated in the verified web data; designers should request the latest material declaration from Intel/Altera for RoHS/REACH confirmation. Not qualified to AEC-Q100 (commercial temperature grade only).
