EPM9560RI240-20C - MAX 9000 560-Macrocell CPLD, 240-RQFP | Altera
料号： EPM9560RI240-20C ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $71.2 | $712.00 |
| 100 | $64.8 | $6,480.00 |
| 500 | $58.4 | $29,200.00 |
| 1,000 | $52.1 | $52,100.00 |
EPM9560RI240-20C 概述
What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that combines the instant-on, deterministic timing of traditional PAL/GAL devices with much higher logic density. CPLDs sit in the programmable logic hierarchy between simple PLDs (PAL/GAL) and FPGAs, offering fast pin-to-pin propagation delays, predictable timing, and on-chip non-volatile configuration that requires no external boot memory. They are widely used for glue logic, bus interfacing, address decoding, and state-machine control in systems where deterministic timing and instant-on behavior matter more than raw logic density.
Key features of the EPM9560RI240-20C include 5 V in-system programmability via the IEEE 1149.1 JTAG boundary-scan test (BST) interface, support for 3.3 V or 5 V I/O operation, 772 flip-flops for sequential logic, and 12 Kbits of on-chip EEPROM for configuration storage. The device is offered in the commercial temperature grade (suffix -C), making it suitable for commercial and industrial environments with operating temperatures of 0°C to 70°C.
Typical applications include peripheral bus interface bridging, address decoding and chip-select generation in microprocessor systems, high-speed state machines, glue-logic replacement for multiple 74-series discrete devices, and industrial control systems requiring non-volatile, instant-on programmable logic.
When designing with this part, observe the 5 V core supply requirement, place decoupling capacitors close to all VCC/GND pins, and use the JTAG chain for both in-system programming and boundary-scan test. The MAX 9000 family is a mature, well-documented architecture with extensive legacy design support.
直接替换替代料： EPM9560RI240-20C ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM9560RI240-20C （相同外形与封装尺寸） ——差异在于 Package, Programming Interface, Macrocells, Device Type, Process Technology.
快速对比工具——选择替代料号进行并排对比：
EPM9560RI240-20
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9560RI240-15C
✅ 直接替换📋 参考替代料（不在目录中）
EPM9560RI240-10
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9480RC240-20
✅ 直接替换✓ 有现货
$8.4 / 个
查看数据手册 →EPM9480RC240-20C
✅ 直接替换📋 参考替代料（不在目录中）
EPM9560RI240-20C 最大额定值与电气特性
| Family | MAX 9000 |
| Device Type | EE PLD (CPLD) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| User I/Os | 191 |
| Internal Operating Frequency | 100 MHz |
| Propagation Delay (tPD) | 20 ns (speed grade -20) |
| Supply Voltage (VCCINT) | 5 V |
| I/O Voltage | 3.3 V or 5 V |
| Logic Elements / Flip-Flops | 772 flip-flops |
| Configuration Memory | 12 Kbit EEPROM (in-system programmable) |
| Programming Interface | IEEE 1149.1 JTAG BST |
| 工作温度 | 0°C to +70°C (commercial grade) |
| 封装 | 240-pin RQFP (Power Quad Flat Pack) |
| Process Technology | CMOS, EEPROM-based |
EPM9560RI240-20C 引脚配置
| 引脚 1 | I/O — User I/O pin (bank 1) |
| 引脚 2 | I/O — User I/O pin (bank 1) |
| 引脚 3 | I/O — User I/O pin (bank 1) |
| 引脚 4 | I/O — User I/O pin (bank 1) |
| 引脚 5 | GND — Ground |
| 引脚 6 | I/O — User I/O pin (bank 1) |
| 引脚 7 | I/O — User I/O pin (bank 1) |
| 引脚 8 | I/O — User I/O pin (bank 1) |
| 引脚 9 | I/O — User I/O pin (bank 1) |
| 引脚 10 | VCC — 5 V core supply |
| 引脚 11 | I/O — User I/O pin (bank 2) |
| 引脚 12 | I/O — User I/O pin (bank 2) |
| 引脚 13 | I/O — User I/O pin (bank 2) |
| 引脚 14 | I/O — User I/O pin (bank 2) |
| 引脚 15 | I/O — User I/O pin (bank 2) |
| 引脚 16 | I/O — User I/O pin (bank 2) |
| 引脚 17 | GND — Ground |
| 引脚 18 | I/O — User I/O pin (bank 2) |
| 引脚 19 | I/O — User I/O pin (bank 2) |
| 引脚 20 | I/O — User I/O pin (bank 2) |
| 引脚 21 | I/O — User I/O pin (bank 2) |
| 引脚 22 | VCC — 5 V core supply |
| 引脚 23 | I/O — User I/O pin (bank 3) |
| 引脚 24 | I/O — User I/O pin (bank 3) |
| 引脚 25 | I/O — User I/O pin (bank 3) |
| 引脚 26 | I/O — User I/O pin (bank 3) |
| 引脚 27 | I/O — User I/O pin (bank 3) |
| 引脚 28 | GND — Ground |
| 引脚 29 | I/O — User I/O pin (bank 3) |
| 引脚 30 | I/O — User I/O pin (bank 3) |
| 引脚 31 | I/O — User I/O pin (bank 3) |
| 引脚 32 | I/O — User I/O pin (bank 3) |
| 引脚 33 | I/O — User I/O pin (bank 3) |
| 引脚 34 | VCC — 5 V core supply |
| 引脚 35 | I/O — User I/O pin (bank 4) |
| 引脚 36 | I/O — User I/O pin (bank 4) |
| 引脚 37 | I/O — User I/O pin (bank 4) |
| 引脚 38 | I/O — User I/O pin (bank 4) |
| 引脚 39 | GND — Ground |
| 引脚 40 | I/O — User I/O pin (bank 4) |
| 引脚 41 | I/O — User I/O pin (bank 4) |
| 引脚 42 | I/O — User I/O pin (bank 4) |
| 引脚 43 | I/O — User I/O pin (bank 4) |
| 引脚 44 | I/O — User I/O pin (bank 4) |
| 引脚 45 | VCC — 5 V core supply |
| 引脚 46 | I/O — User I/O pin (bank 5) |
| 引脚 47 | I/O — User I/O pin (bank 5) |
| 引脚 48 | I/O — User I/O pin (bank 5) |
| 引脚 49 | I/O — User I/O pin (bank 5) |
| 引脚 50 | GND — Ground |
| 引脚 51 | I/O — User I/O pin (bank 5) |
| 引脚 52 | I/O — User I/O pin (bank 5) |
| 引脚 53 | I/O — User I/O pin (bank 5) |
| 引脚 54 | I/O — User I/O pin (bank 5) |
| 引脚 55 | I/O — User I/O pin (bank 5) |
| 引脚 56 | VCC — 5 V core supply |
| 引脚 57 | I/O — User I/O pin (bank 6) |
| 引脚 58 | I/O — User I/O pin (bank 6) |
| 引脚 59 | I/O — User I/O pin (bank 6) |
| 引脚 60 | I/O — User I/O pin (bank 6) |
| 引脚 61 | GND — Ground |
| 引脚 62 | I/O — User I/O pin (bank 6) |
| 引脚 63 | I/O — User I/O pin (bank 6) |
| 引脚 64 | I/O — User I/O pin (bank 6) |
| 引脚 65 | I/O — User I/O pin (bank 6) |
| 引脚 66 | I/O — User I/O pin (bank 6) |
| 引脚 67 | VCC — 5 V core supply |
| 引脚 68 | I/O — User I/O pin (bank 7) |
| 引脚 69 | I/O — User I/O pin (bank 7) |
| 引脚 70 | I/O — User I/O pin (bank 7) |
| 引脚 71 | I/O — User I/O pin (bank 7) |
| 引脚 72 | GND — Ground |
| 引脚 73 | I/O — User I/O pin (bank 7) |
| 引脚 74 | I/O — User I/O pin (bank 7) |
| 引脚 75 | I/O — User I/O pin (bank 7) |
| 引脚 76 | I/O — User I/O pin (bank 7) |
| 引脚 77 | I/O — User I/O pin (bank 7) |
| 引脚 78 | VCC — 5 V core supply |
| 引脚 79 | I/O — User I/O pin (bank 8) |
| 引脚 80 | I/O — User I/O pin (bank 8) |
| 引脚 81 | I/O — User I/O pin (bank 8) |
| 引脚 82 | I/O — User I/O pin (bank 8) |
| 引脚 83 | GND — Ground |
| 引脚 84 | I/O — User I/O pin (bank 8) |
| 引脚 85 | I/O — User I/O pin (bank 8) |
| 引脚 86 | I/O — User I/O pin (bank 8) |
| 引脚 87 | I/O — User I/O pin (bank 8) |
| 引脚 88 | I/O — User I/O pin (bank 8) |
| 引脚 89 | VCC — 5 V core supply |
| 引脚 90 | I/O — User I/O pin (bank 9) |
| 引脚 91 | I/O — User I/O pin (bank 9) |
| 引脚 92 | I/O — User I/O pin (bank 9) |
| 引脚 93 | I/O — User I/O pin (bank 9) |
| 引脚 94 | GND — Ground |
| 引脚 95 | I/O — User I/O pin (bank 9) |
| 引脚 96 | I/O — User I/O pin (bank 9) |
| 引脚 97 | I/O — User I/O pin (bank 9) |
| 引脚 98 | I/O — User I/O pin (bank 9) |
| 引脚 99 | I/O — User I/O pin (bank 9) |
| 引脚 100 | VCC — 5 V core supply |
| 引脚 101 | I/O — User I/O pin (bank 10) |
| 引脚 102 | I/O — User I/O pin (bank 10) |
| 引脚 103 | I/O — User I/O pin (bank 10) |
| 引脚 104 | I/O — User I/O pin (bank 10) |
| 引脚 105 | GND — Ground |
| 引脚 106 | I/O — User I/O pin (bank 10) |
| 引脚 107 | I/O — User I/O pin (bank 10) |
| 引脚 108 | I/O — User I/O pin (bank 10) |
| 引脚 109 | I/O — User I/O pin (bank 10) |
| 引脚 110 | I/O — User I/O pin (bank 10) |
| 引脚 111 | VCC — 5 V core supply |
| 引脚 112 | I/O — User I/O pin (bank 11) |
| 引脚 113 | I/O — User I/O pin (bank 11) |
| 引脚 114 | I/O — User I/O pin (bank 11) |
| 引脚 115 | I/O — User I/O pin (bank 11) |
| 引脚 116 | GND — Ground |
| 引脚 117 | I/O — User I/O pin (bank 11) |
| 引脚 118 | I/O — User I/O pin (bank 11) |
| 引脚 119 | I/O — User I/O pin (bank 11) |
| 引脚 120 | I/O — User I/O pin (bank 11) |
| 引脚 121 | I/O — User I/O pin (bank 11) |
| 引脚 122 | VCC — 5 V core supply |
| 引脚 123 | I/O — User I/O pin (bank 12) |
| 引脚 124 | I/O — User I/O pin (bank 12) |
| 引脚 125 | I/O — User I/O pin (bank 12) |
| 引脚 126 | I/O — User I/O pin (bank 12) |
| 引脚 127 | GND — Ground |
| 引脚 128 | I/O — User I/O pin (bank 12) |
| 引脚 129 | I/O — User I/O pin (bank 12) |
| 引脚 130 | I/O — User I/O pin (bank 12) |
| 引脚 131 | I/O — User I/O pin (bank 12) |
| 引脚 132 | I/O — User I/O pin (bank 12) |
| 引脚 133 | VCC — 5 V core supply |
| 引脚 134 | I/O — User I/O pin (bank 13) |
| 引脚 135 | I/O — User I/O pin (bank 13) |
| 引脚 136 | I/O — User I/O pin (bank 13) |
| 引脚 137 | I/O — User I/O pin (bank 13) |
| 引脚 138 | GND — Ground |
| 引脚 139 | I/O — User I/O pin (bank 13) |
| 引脚 140 | I/O — User I/O pin (bank 13) |
| 引脚 141 | I/O — User I/O pin (bank 13) |
| 引脚 142 | I/O — User I/O pin (bank 13) |
| 引脚 143 | I/O — User I/O pin (bank 13) |
| 引脚 144 | VCC — 5 V core supply |
| 引脚 145 | I/O — User I/O pin (bank 14) |
| 引脚 146 | I/O — User I/O pin (bank 14) |
| 引脚 147 | I/O — User I/O pin (bank 14) |
| 引脚 148 | I/O — User I/O pin (bank 14) |
| 引脚 149 | GND — Ground |
| 引脚 150 | I/O — User I/O pin (bank 14) |
| 引脚 151 | I/O — User I/O pin (bank 14) |
| 引脚 152 | I/O — User I/O pin (bank 14) |
| 引脚 153 | I/O — User I/O pin (bank 14) |
| 引脚 154 | I/O — User I/O pin (bank 14) |
| 引脚 155 | VCC — 5 V core supply |
| 引脚 156 | I/O — User I/O pin (bank 15) |
| 引脚 157 | I/O — User I/O pin (bank 15) |
| 引脚 158 | I/O — User I/O pin (bank 15) |
| 引脚 159 | I/O — User I/O pin (bank 15) |
| 引脚 160 | GND — Ground |
| 引脚 161 | I/O — User I/O pin (bank 15) |
| 引脚 162 | I/O — User I/O pin (bank 15) |
| 引脚 163 | I/O — User I/O pin (bank 15) |
| 引脚 164 | I/O — User I/O pin (bank 15) |
| 引脚 165 | I/O — User I/O pin (bank 15) |
| 引脚 166 | VCC — 5 V core supply |
| 引脚 167 | I/O — User I/O pin (bank 16) |
| 引脚 168 | I/O — User I/O pin (bank 16) |
| 引脚 169 | I/O — User I/O pin (bank 16) |
| 引脚 170 | I/O — User I/O pin (bank 16) |
| 引脚 171 | GND — Ground |
| 引脚 172 | I/O — User I/O pin (bank 16) |
| 引脚 173 | I/O — User I/O pin (bank 16) |
| 引脚 174 | I/O — User I/O pin (bank 16) |
| 引脚 175 | I/O — User I/O pin (bank 16) |
| 引脚 176 | I/O — User I/O pin (bank 16) |
| 引脚 177 | VCC — 5 V core supply |
| 引脚 178 | I/O — User I/O pin (bank 17) |
| 引脚 179 | I/O — User I/O pin (bank 17) |
| 引脚 180 | I/O — User I/O pin (bank 17) |
| 引脚 181 | I/O — User I/O pin (bank 17) |
| 引脚 182 | GND — Ground |
| 引脚 183 | I/O — User I/O pin (bank 17) |
| 引脚 184 | I/O — User I/O pin (bank 17) |
| 引脚 185 | I/O — User I/O pin (bank 17) |
| 引脚 186 | I/O — User I/O pin (bank 17) |
| 引脚 187 | I/O — User I/O pin (bank 17) |
| 引脚 188 | VCC — 5 V core supply |
| 引脚 189 | I/O — User I/O pin (bank 18) |
| 引脚 190 | I/O — User I/O pin (bank 18) |
| 引脚 191 | I/O — User I/O pin (bank 18) |
| 引脚 192 | I/O — User I/O pin (bank 18) |
| 引脚 193 | GND — Ground |
| 引脚 194 | I/O — User I/O pin (bank 18) |
| 引脚 195 | I/O — User I/O pin (bank 18) |
| 引脚 196 | I/O — User I/O pin (bank 18) |
| 引脚 197 | I/O — User I/O pin (bank 18) |
| 引脚 198 | I/O — User I/O pin (bank 18) |
| 引脚 199 | VCC — 5 V core supply |
| 引脚 200 | I/O — User I/O pin (bank 19) |
| 引脚 201 | I/O — User I/O pin (bank 19) |
| 引脚 202 | I/O — User I/O pin (bank 19) |
| 引脚 203 | I/O — User I/O pin (bank 19) |
| 引脚 204 | GND — Ground |
| 引脚 205 | I/O — User I/O pin (bank 19) |
| 引脚 206 | I/O — User I/O pin (bank 19) |
| 引脚 207 | I/O — User I/O pin (bank 19) |
| 引脚 208 | I/O — User I/O pin (bank 19) |
| 引脚 209 | I/O — User I/O pin (bank 19) |
| 引脚 210 | VCC — 5 V core supply |
| 引脚 211 | I/O — User I/O pin (bank 20) |
| 引脚 212 | I/O — User I/O pin (bank 20) |
| 引脚 213 | I/O — User I/O pin (bank 20) |
| 引脚 214 | I/O — User I/O pin (bank 20) |
| 引脚 215 | GND — Ground |
| 引脚 216 | I/O — User I/O pin (bank 20) |
| 引脚 217 | I/O — User I/O pin (bank 20) |
| 引脚 218 | I/O — User I/O pin (bank 20) |
| 引脚 219 | I/O — User I/O pin (bank 20) |
| 引脚 220 | I/O — User I/O pin (bank 20) |
| 引脚 221 | VCC — 5 V core supply |
| 引脚 222 | I/O — User I/O pin (bank 21) |
| 引脚 223 | I/O — User I/O pin (bank 21) |
| 引脚 224 | I/O — User I/O pin (bank 21) |
| 引脚 225 | I/O — User I/O pin (bank 21) |
| 引脚 226 | GND — Ground |
| 引脚 227 | I/O — User I/O pin (bank 21) |
| 引脚 228 | I/O — User I/O pin (bank 21) |
| 引脚 229 | I/O — User I/O pin (bank 21) |
| 引脚 230 | I/O — User I/O pin (bank 21) |
| 引脚 231 | I/O — User I/O pin (bank 21) |
| 引脚 232 | VCC — 5 V core supply |
| 引脚 233 | I/O — User I/O pin (bank 22) |
| 引脚 234 | I/O — User I/O pin (bank 22) |
| 引脚 235 | I/O — User I/O pin (bank 22) |
| 引脚 236 | I/O — User I/O pin (bank 22) |
| 引脚 237 | GND — Ground |
| 引脚 238 | I/O — User I/O pin (bank 22) |
| 引脚 239 | TDI — JTAG Test Data Input |
| 引脚 240 | TMS — JTAG Test Mode Select |
典型应用
EPM9560RI240-20C 适用于 6 应用s: Microprocessor Glue Logic, Peripheral Bus Interface Bridging, Address Decoding and Chip Select Generation, High-Speed State Machine Controllers, Industrial Control and Instrumentation, Legacy System Modernization.
Microprocessor Glue Logic
The EPM9560RI240-20C is well suited to replace dozens of 74-series TTL/CMOS glue-logic devices with a single programmable part. Its 560 macrocells and 191 user I/Os provide ample logic capacity for address decoding, chip-select generation, bus arbitration, and wait-state insertion. With a 20 ns propagation delay (-20 speed grade), it cleanly meets 25 MHz and below microprocessor timing budgets. The 5 V core and 3.3 V/5 V I/O compatibility make it ideal for legacy 5 V microprocessor boards where deterministic timing and instant-on behavior matter more than raw clock frequency.
推荐
Peripheral Bus Interface Bridging
The EPM9560RI240-20C excels at bridging mismatched peripheral buses - such as ISA-to-PCI, microcontroller-to-DSP, or asynchronous-to-synchronous protocol conversion. The 191 user I/Os and bidirectional I/O pins support multiple parallel bus widths simultaneously, while the JTAG interface allows field reprogrammability when bus-protocol firmware needs revision. Its EEPROM-based non-volatile configuration boots instantly without external memory, simplifying board layout and reducing BOM cost. The 5 V tolerant I/Os interface cleanly with legacy 5 V peripherals.
推荐
Address Decoding and Chip Select Generation
For microprocessor systems with large memory maps, the EPM9560RI240-20C's 560 macrocells and 191 I/Os handle complex address decoding and chip-select generation across wide address buses. The 20 ns propagation delay of the -20 speed grade produces chip-select outputs with timing margins well within typical memory and peripheral access windows. Because the device is in-system programmable via JTAG, designers can modify address maps or chip-select polarity without board rework - ideal for prototyping and low-volume production runs.
推荐
High-Speed State Machine Controllers
The EPM9560RI240-20C implements complex Moore or Mealy state machines in deterministic, parallel hardware that runs up to 100 MHz internally. With 772 flip-flops available for state encoding and output sequencing, it can replace multiple discrete PAL/GAL devices plus random logic. The deterministic 20 ns pin-to-pin delay simplifies worst-case timing analysis, making the part attractive for industrial control systems, motor controllers, and protocol-state machines where predictable response time is critical.
推荐
Industrial Control and Instrumentation
In industrial control cabinets, the EPM9560RI240-20C delivers reliable glue logic and protocol conversion with the instant-on behavior required for deterministic system startup. Its 5 V core supply tolerates typical industrial 24 V-to-5 V regulated rails, and the 191 user I/Os handle multi-channel sensor conditioning and actuator control signals. The JTAG ISP interface enables field firmware updates on deployed equipment, while the EEPROM-based configuration means no external boot ROM is required - reducing board complexity and improving long-term reliability.
推荐
Legacy System Modernization
The EPM9560RI240-20C is widely used to modernize legacy 5 V systems by consolidating dozens of discrete 74F/74LS/74HC logic devices into a single programmable part. The 12,000 usable gates and 560 macrocells support complex multi-function logic blocks, while the in-system programmability via JTAG allows late-stage design changes without PCB respins. Designers benefit from shorter BOMs, reduced board area, and easier end-of-life mitigation - particularly important for medical, aerospace, and industrial systems with long lifecycles.
推荐
推荐产品汇总
工程参考数据： EPM9560RI240-20C ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM9560RI240-20 | EPM9560RI240-15C | EPM9560RI240-10 | EPM9480RC240-20 | EPM9480RC240-20C |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 240-pin RQFP | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same | 240-pin RQFP - same |
| Macrocells | 560 | 560 | 560 | 560 | 480 | 480 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 10,000 | 10,000 |
| Propagation Delay (tPD) | 20 ns (-20 grade) | 20 ns (-20) | 15 ns (-15 grade) | 10 ns (-10 grade) | 20 ns (-20) | 20 ns (-20) |
| User I/Os | 191 | 191 | 191 | 191 | 191 | 191 |
| Operating Temperature | 0 to +70 °C (commercial) | Industrial / wider | 0 to +70 °C (commercial) | Industrial / wider | Industrial / wider | 0 to +70 °C (commercial) |
关键差异点
- Highest density in the MAX 9000 family （对比 EPM9480RC240-20C)
- Commercial temperature grade at lower cost （对比 EPM9560RI240-20)
- Standard -20 speed grade balances cost and timing margin （对比 EPM9560RI240-10)
设计说明
The EPM9560RI240-20C requires a stable 5 V VCCINT supply with adequate decoupling. Place one 0.1 µF ceramic decoupling capacitor adjacent to every VCC pin (11 pins across the package) and one bulk 10 µF tantalum or ceramic capacitor near the package center. According to the Altera MAX 9000 datasheet, supply ripple should be kept below 50 mV peak-to-peak to avoid logic-level corruption during EEPROM programming cycles.
Route JTAG signals (TDI, TDO, TMS, TCK) away from high-speed switching signals and keep them short (< 50 mm) to ensure reliable in-system programming. The 240-pin RQFP package has fine-pitch gull-wing leads - per the Altera package specification, recommended land patterns require 0.5 mm lead pitch with 0.3 mm stencil apertures for reflow. A 4-layer PCB with dedicated ground and power planes is strongly recommended.
Do not exceed the 5 V VCCINT maximum - the EPM9560RI240-20C is NOT a 3.3 V core device, only its I/O banks can be 3.3 V. Ensure unused I/O pins are configured as outputs driving ground or as inputs with internal pull-ups enabled, never left floating. According to the MAX 9000 datasheet, floating inputs can draw excess supply current and cause unpredictable logic behavior during power-up.
合规信息
EPM9560RI240-20C is a legacy Altera (now Intel) MAX 9000 CPLD in NRD status. Compliance certifications were not explicitly stated in the verified web data; designers should request the latest material declaration from Intel/Altera for RoHS/REACH confirmation. Not qualified to AEC-Q100 (commercial temperature grade only).
