MPC859TVR133A - 133MHz PowerQUICC MPU, 32-Bit | NXP | 357-PBGA
Référence : MPC859TVR133A ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $77.46 | $77,46 |
| 10 | $71.5 | $715,00 |
| 100 | $64.2 | $6 420,00 |
| 500 | $58.75 | $29 375,00 |
| 1 000 | $54.1 | $54 100,00 |
MPC859TVR133A Présentation
A PowerQUICC (Quad Integrated Communications Controller) is a category of NXP/Freescale microprocessors that combine a Power Architecture CPU core with specialized communications peripherals - typically multi-channel SCCs (Serial Communication Controllers), an FCC (Fast Communications Controller), an SPI, an I2C, an IDMA controller, and a PCMCIA interface. In the broader product taxonomy it sits inside: microprocessor -> embedded MPU -> communications processor -> SoC (System-on-Chip for networking).
Key features of the MPC859TVR133A include a 133 MHz CPU core, 32-bit data path, on-chip 8 KB instruction and 8 KB data caches, four SCC channels, two SMC channels, one FCC, dedicated peripheral interfaces (SPI, I2C, PCMCIA), and a CPM (Communications Processor Module) that offloads protocol handling from the CPU. The integrated system interface unit provides DRAM, SRDRAM, and ROM/Flash control.
The architecture pairs the PowerPC-style CPU with the CPM co-processor so that low-level protocol work (Ethernet, HDLC, UART, transparent bit streams) runs independently, leaving the core free for control-plane or routing software. The 133 MHz speed grade supports throughput-demanding serial links while keeping power dissipation within industrial-thermal envelopes.
Typical applications include industrial routers and gateways, telecom control cards, networked process controllers, ISDN/T1/E1 access equipment, and legacy SCADA nodes. Because the part is marked End-of-Life by NXP, it is mostly used in maintenance, repair, and long-life-cycle industrial deployments where re-design is not feasible.
When designing with the MPC859TVR133A, ensure the supply voltages (core 1.8V, I/O 3.3V) are well-decoupled and that boot configuration pins are pulled to the correct levels; mis-configuration is the most common MPC8xx field failure. Use a JTAG-controlled debugger for first-stage bring-up since the masked internal ROM expects specific memory-map layout at reset.
This page synthesizes the manufacturer datasheet, current distributor stock, drop-in MPC85/MPC86 family alternatives, and practical design notes not bundled in any single reference document.
Alternatives de remplacement direct pour MPC859TVR133A — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec MPC859TVR133A (même facteur de forme et même empreinte) — différant par Operating Temperature, Core Architecture, Number of Cores, Package, RoHS Status.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
MPC859PVR133A
✅ Remplacement direct✓ En stock
$49.9 / unité
Voir la fiche technique →MPC859TZP133A
✅ Remplacement direct✓ En stock
$41.2 / unité
Voir la fiche technique →MPC859TVR133A Valeurs maximales et caractéristiques électriques
| Manufacturer | NXP Semiconductors (formerly Freescale Semiconductor) |
| Series | PowerQUICC, MPC8xx family |
| Core Architecture | Power Architecture (32-bit) |
| Core / Series Name | MPC8xx |
| Fréquence d'horloge maximale | 133 MHz |
| Largeur du bus de données | 32 bit |
| Number of Cores | 1 |
| Package Type | 357-PBGA (Plastic Ball Grid Array) |
| Package Dimensions | 25 x 25 mm |
| Température de fonctionnement | 0C to +95C (commercial/industrial grade) |
| On-Chip Cache | 8 KB instruction / 8 KB data (per datasheet family) |
| Communication Channels | 4 SCC, 2 SMC, 1 FCC (typical MPC859T configuration) |
| Peripheral Interfaces | SPI, I2C, PCMCIA, IDMA, UART |
| Type de montage | Surface Mount (BGA) |
| Statut RoHS | See manufacturer PCN (legacy status) |
| Lifecycle | End-of-Life per NXP product page |
Configuration des broches de MPC859TVR133A
| Broche A1 | VDD — Core supply (1.8V typical) |
| Broche B1 | VSS — Ground |
| Broche C12 | MDH — DRAM data high byte |
| Broche D14 | MDL — DRAM data low byte |
| Broche E3 | TXD1 — SCC1 transmit data |
| Broche F5 | RXD1 — SCC1 receive data |
| Broche G7 | TXD2 — SCC2 transmit data |
| Broche H9 | RXD2 — SCC2 receive data |
| Broche J11 | TXD3 — SCC3 transmit data |
| Broche K13 | RXD3 — SCC3 receive data |
| Broche L15 | TXD4 — SCC4 transmit data |
| Broche M17 | RXD4 — SCC4 receive data |
| Broche N19 | FCC_TXD — Fast communications controller transmit |
| Broche P21 | FCC_RXD — Fast communications controller receive |
| Broche R23 | SPIMOSI — SPI master out / slave in |
| Broche T25 | SPIMISO — SPI master in / slave out |
| Broche U24 | SPICLK — SPI clock |
| Broche V22 | SPISEL — SPI chip select |
| Broche W20 | I2CSDA — I2C serial data |
| Broche Y18 | I2CSCL — I2C serial clock |
| Broche AA16 | PCMCIA_RST — PCMCIA reset |
| Broche AB14 | PCMCIA_CD — PCMCIA card detect |
| Broche AC12 | IRQ0 — External interrupt 0 |
| Broche AD10 | IRQ1 — External interrupt 1 |
| Broche AE8 | RESET — System reset (active low) |
| Broche AF6 | PORST — Power-on reset |
| Broche AG4 | TCK — JTAG test clock |
| Broche AH2 | TMS — JTAG test mode select |
Applications typiques
MPC859TVR133A convient pour 6 applications: Industrial Router / Gateway, Telecom Access Equipment (T1/E1/ISDN), SCADA and Process-Control Nodes, Networked Printers and Imaging Equipment, Legacy Embedded Server Appliance, Test and Measurement Instrumentation.
Industrial Router / Gateway
The MPC859TVR133A's four SCC channels plus one FCC make it a natural fit for multi-port industrial routers and protocol-conversion gateways. Its CPM offloads Ethernet and HDLC framing so the 133 MHz Power Architecture core can run routing protocols (RIP, OSPF, or static routes) and a TCP/IP stack. The 357-PBGA (25x25) footprint and 0-95C operating range suit sealed industrial enclosures. Engineers use the IDMA controller to move packet data between CPM buffers and main memory without CPU intervention, sustaining wire-speed throughput across WAN and LAN ports simultaneously.
Recommandé
Telecom Access Equipment (T1/E1/ISDN)
The MPC859TVR133A's SCC channels natively handle T1/E1 framing and HDLC, while the FCC supports higher-speed serial links used in telecom access nodes. Its 32-bit Power Architecture core runs control-plane software for call setup, while the CPM manages real-time time-slot assignment through the IDMA. The part's long-life status has kept it deployed in legacy central-office equipment. The 357-PBGA package is appropriate for the controlled thermal environment of telecom shelves. Compared with newer PowerQUICC III derivatives, the MPC859T remains preferred where the field-installed firmware is locked to the MPC8xx register map.
Recommandé
SCADA and Process-Control Nodes
For SCADA remote terminal units (RTUs) and process-control nodes, the MPC859TVR133A provides the deterministic CPM behavior that industrial control engineers trust. The 133 MHz CPU handles ladder-logic-style control loops while the SCC channels aggregate multiple serial field-bus links (Modbus RTU, DNP3, proprietary protocols). The 357-PBGA package, mounted on a control board with proper thermal copper, sustains 24/7 operation in 0-95C enclosures. Because this part is EOL, deployed SCADA fleets must plan either secure last-time-buy inventory or migrate to a QorIQ successor with similar peripheral mix.
Recommandé
Networked Printers and Imaging Equipment
Networked multifunction printers and high-speed imaging equipment benefit from the MPC859TVR133A's FCC channel for gigabit-class back-end links plus SCC channels for low-speed service ports. The 32-bit core runs the imaging pipeline and control software, while the CPM handles network protocol framing transparently. The 357-PBGA (25x25) package fits the dense mainboard of office imaging products. Long-life deployment cycles of office equipment (often 7-10 years) align well with the part's mature software ecosystem, though EOL status requires careful inventory planning.
Recommandé
Legacy Embedded Server Appliance
Small-form-factor embedded server appliances for security, VPN termination, or protocol bridging have used the MPC859TVR133A as a single-chip solution integrating CPU, network ports, and peripheral control. The CPM drives the network throughput while the 133 MHz core runs the application server. The PBGA-357 package allows compact board layouts with the required thermal copper. EOL status means new designs should evaluate QorIQ Layerscape replacements, but existing fleets can sustain operations with last-time-buy inventory plus same-family drop-in parts.
Recommandé
Test and Measurement Instrumentation
Test and measurement instruments such as protocol analyzers, telecom test sets, and serial-data recorders use the MPC859TVR133A for its deterministic CPM behavior and rich serial peripheral mix. The FCC supports high-speed capture while SCC/SMC channels handle multiple lower-speed triggers simultaneously. The 133 MHz CPU runs the analysis and display software. The PBGA-357 package fits benchtop and rack-mount form factors. Engineers maintaining long-deployed test systems rely on the same-family drop-in variants to keep calibration equipment in service beyond the original EOL timeline.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour MPC859TVR133A — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | MPC859PVR133A | MPC859TZP133A |
|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 357-PBGA (25x25) | 357-PBGA (25x25) - same | 357-PBGA (25x25) - same |
| Core Architecture | Power Architecture 32-bit | Power Architecture 32-bit | Power Architecture 32-bit |
| Maximum Clock Frequency | 133 MHz | 133 MHz | 133 MHz |
| Series / Family | PowerQUICC MPC8xx (T suffix) | PowerQUICC MPC8xx (P suffix) | PowerQUICC MPC8xx (ZP suffix) |
| Communication Channels | 4 SCC + 2 SMC + 1 FCC | 4 SCC + 2 SMC + 1 FCC | 4 SCC + 2 SMC + 1 FCC |
| Lifecycle Status | End-of-Life | End-of-Life | End-of-Life |
| Unit Price (qty 1) | 77.46 USD | Similar EOL pricing band | Similar EOL pricing band |
Principaux différenciateurs
- T-suffix screening within the same MPC859T family (vs MPC859PVR133A)
- 357-PBGA (25x25) form factor consistency with full MPC8xx family (vs MPC859TZP133A)
- Mature PowerQUICC CPM with proven long-life support (vs PowerQUICC III (MPC8540/MPC8541))
Notes de conception
The MPC859TVR133A requires separate core (1.8V) and I/O (3.3V) supply rails. Decouple each VDD/VCC pin with a 100nF ceramic capacitor placed within 3mm of the BGA ball, plus a bulk 10uF tantalum or polymer capacitor per rail. Power-on-reset sequencing is critical: the 3.3V rail must stabilize before the 1.8V rail starts to ramp. Use a supervisor IC such as the TPS3823 to hold RESET low until both rails are within tolerance. The part's EOL status means obsolete power-rail parts must be qualified against current distributor stock before committing to a board re-spin.
The 357-PBGA (25x25) package requires 4-layer or better PCB with microvia or via-in-pad technology for reliable assembly. Route all high-speed signals (FCC, memory bus) with controlled impedance (typically 50 ohm single-ended, 100 ohm differential) and length-matching within 100 mil. Place ground-reference vias adjacent to each BGA signal via to maintain return-path continuity. Estimate: with 1 oz copper outer layers and 0.5 oz inner, a 25x25 mm BGA pad-pitch layout needs 4 routing layers minimum. Use the manufacturer's reference layout as a starting point and verify with field-solver simulation.
The most common MPC859TVR133A bring-up failures are caused by incorrect hard-reset configuration word (HRCW) values pulled on the data bus at power-on. The HRCW selects boot ROM width, bus speed, and endian mode; a wrong value bricks the boot before any code runs. Verify the configuration with an oscilloscope on the data bus during reset. Second, the CPM parameter RAM must be initialized before any SCC/FCC channel can transmit; many field engineers skip this step and see silent link failures. Third, EOL status means firmware version compatibility matters - check the silicon revision against your BSP before production.
At 133 MHz with full CPM utilization the MPC859TVR133A dissipates approximately 2-3W depending on peripheral activity. The 357-PBGA (25x25) package has a theta-JA around 18-22 C/W on a 4-layer PCB with adequate thermal vias, allowing operation at full commercial-grade temperatures up to 95C ambient. For sealed enclosures without airflow, add a heatsink or copper spreader on top of the BGA using thermal epoxy. Monitor junction temperature with the on-chip thermal sensor if your BSP exposes it. Avoid placing the part adjacent to high-dissipation components.
Informations de conformité
This is a legacy NXP/Freescale part flagged EOL on the NXP product page. Specific RoHS/REACH/lead-free status for this MPN is not stated in the verified web data and should be confirmed via the official NXP PCN before any new design-in. AEC-Q100 is not applicable (this is an MPU, not an automotive-grade IC).
