CDK8307AILP64 vs CDK8307CILP64 तुलना
विस्तृत दोनों ओर की तुलना CDK8307AILP64 द्वारा MaxLinear और CDK8307CILP64 द्वारा MaxLinear. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
MaxLinear
CDK8307AILP64 - 12/13-bit Octal Ultra-Low Power LVDS ADC | MaxLinear
CDK8307AILP64 ✓ सक्रियMaxLinear
CDK8307CILP64 - 12/13-bit 65MSPS Octal ADC, LVDS Output | MaxLinear
CDK8307CILP64 ✓ सक्रियविशेषता तुलना
| पैरामीटर | CDK8307AILP64 | CDK8307CILP64 |
|---|---|---|
| ब्रांड | MaxLinear | MaxLinear |
| श्रेणी | ADC/DAC | ADC/DAC |
| लाइफसाइकिल स्थिति | सक्रिय | सक्रिय |
| रेज़ोल्यूशन | 12/13-bit (selectable) | 12/13-bit (selectable) |
| Number of Channels | 8 (simultaneous sampling) | 8 (simultaneous sampling) |
| Sample Rate Range | 20 / 40 / 50 / 65 / 80 MSPS | — |
| Architecture | Pipelined ADC with proprietary core | Proprietary pipeline ADC |
| Output Interface | Serial LVDS | — |
| Reference | Internal reference (integrated) | Internal (integrated bandgap) |
| सप्लाई वोल्टेज | [DATA_NEEDED: supply voltage] | — |
| Power Dissipation (Typ) | Ultra-low power (per-channel shutdown) | — |
| Shutdown Modes | Per-channel + full-chip idle (via external pin) | — |
| Control Interface | Serial programming interface (SPI-style) | SPI-compatible serial |
| FPGA Compatibility | Designed to interface with major FPGA vendors | — |
| पैकेज | 64-pin QFN (ILP64) | 64-pin LQFP (LP64) |
| माउंटिंग प्रकार | Surface Mount | Surface Mount |
| ऑपरेटिंग तापमान रेंज | [DATA_NEEDED: temperature range] | [DATA_NEEDED: operating temperature range] |
| RoHS स्थिति | Compliant | Compliant (per MaxLinear product page) |
| Original Brand | Cadeka / Exar (now MaxLinear) | — |
| Sample Rate | — | 65 MSPS maximum (20/40/50/65 MSPS grades) |
| Digital Output Interface | — | Serial LVDS |
| Input Type | — | Differential analog inputs |
| Power Profile | — | Ultra-low power (per-channel) |
| Supply Voltage (AVDD) | — | [DATA_NEEDED: AVDD nominal] |
| Supply Voltage (DRVDD/LVDS) | — | [DATA_NEEDED: DRVDD nominal] |
| ENOB | — | [DATA_NEEDED: effective number of bits] |
| SNR | — | [DATA_NEEDED: signal-to-noise ratio] |
| SFDR | — | [DATA_NEEDED: spurious-free dynamic range] |