EP1810GM883 vs EP1810JC-35 तुलना
विस्तृत दोनों ओर की तुलना EP1810GM883 द्वारा Altera और EP1810JC-35 द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP1810GM883 | EP1810JC-35 |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | Classic EPLD (EP1810 series) | — |
| Device Type | UV-Erasable Programmable Logic Device (EPLD) | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Macrocells | 48 | — |
| Dedicated Inputs | 12 | — |
| User I/O Pins | 48 | — |
| Total Terminals | 68 | — |
| Global Clocks | 4 | — |
| Supply Voltage (Vcc) | 4.5 V to 5.5 V (nominal 5 V) | 5 V (nominal) |
| Propagation Delay (tpd) | 45 ns (max) | 35 ns (max) |
| Maximum Toggle Frequency (fmax) | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] | — |
| Process Technology | CMOS, UV-erasable | CMOS |
| पैकेज | 68-Pin Ceramic Pin Grid Array (PGA) | — |
| ऑपरेटिंग तापमान | -55C to +125C (MIL-STD-883 Class B) | — |
| Screening | MIL-STD-883 Class B (suffix '883' denotes MIL processing) | — |
| माउंटिंग प्रकार | Through-Hole (PGA socket) | Surface Mount (J-Lead) |
| RoHS स्थिति | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] | Compliant (per Altera listing) |
| Lead-Free | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] | — |
| Device Family | — | Classic EPLD (EP1810) |
| Number of Macrocells | — | 48 |
| अधिकतम क्लॉक फ़्रीक्वेंसी | — | [DATA_NEEDED: fmax for this speed grade] |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Package Type | — | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| ऑपरेटिंग तापमान रेंज | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |