EP1810GM883 vs EP1810JC-35 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810GM883 disebabkan oleh Altera dan EP1810JC-35 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP1810GM883 EP1810JC-35
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family Classic EPLD (EP1810 series) —
Device Type UV-Erasable Programmable Logic Device (EPLD) UV-Erasable Complex PLD (UV PLD / CPLD)
Macrocells 48 —
Dedicated Inputs 12 —
User I/O Pins 48 —
Total Terminals 68 —
Global Clocks 4 —
Supply Voltage (Vcc) 4.5 V to 5.5 V (nominal 5 V) 5 V (nominal)
Propagation Delay (tpd) 45 ns (max) 35 ns (max)
Maximum Toggle Frequency (fmax) [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] —
Process Technology CMOS, UV-erasable CMOS
Kemasan 68-Pin Ceramic Pin Grid Array (PGA) —
Suhu Operasi -55C to +125C (MIL-STD-883 Class B) —
Screening MIL-STD-883 Class B (suffix '883' denotes MIL processing) —
Jenis Pemasangan Through-Hole (PGA socket) Surface Mount (J-Lead)
Status RoHS [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] Compliant (per Altera listing)
Lead-Free [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] —
Device Family — Classic EPLD (EP1810)
Number of Macrocells — 48
Frekuensi Klock Maksimum — [DATA_NEEDED: fmax for this speed grade]
Maximum Supply Voltage — 5.25 V (per distributor listing)
Package Type — CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ)
Number of Terminals — 68
Terminal Form — J-Bend
Gambaran Suhu Operasi — 0°C to 70°C (Commercial)
Temperature Grade — Commercial
Erasure Method — UV (quartz-windowed ceramic package)
Lead-Free Status — Lead-free (per distributor listing)
Logic Architecture — Programmable AND/OR array with macrocell outputs

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