EP910PC-15 vs EP910PC-15T तुलना
विस्तृत दोनों ओर की तुलना EP910PC-15 द्वारा Altera और EP910PC-15T द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910PC-15 | EP910PC-15T |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Usable Gates | 900 | — |
| Macrocells | 24 | — |
| Maximum Pin-to-Pin Delay (tpd) | 15 ns | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (nominal) |
| Supply Current (Icc) | 80 mA typical | — |
| Dedicated Inputs | 10 | — |
| Dedicated I/O Pins | 12 | — |
| ऑपरेटिंग तापमान | 0C to +70C (commercial) | 0C to +70C (commercial) |
| पैकेज | 24-pin PDIP (PDIP-24, 0.300 inch) | 40-pin PDIP (Plastic DIP) |
| माउंटिंग प्रकार | Through-Hole | Through-hole (DIP) |
| Process Technology | CMOS, UV-erasable | — |
| Programming Method | Altera Logic Programmer card | JEDEC fuse map via Altera LogicMap / MAX+PLUS II |
| RoHS स्थिति | [DATA_NEEDED: RoHS status - EP910 is a legacy through-hole part, likely non-RoHS] | [DATA_NEEDED: RoHS compliance status] |
| MSL स्तर | Not applicable (through-hole) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | — | 24 |
| Dedicated Input Pins | — | 10 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Speed Grade | — | -15 (15 ns) |
| Technology | — | CMOS, UV-erasable / OTP |
| Output Drive Current | — | [DATA_NEEDED: IOL per output] |
| Logic Capacity | — | 24 macrocells / 72 product terms (typical Classic architecture) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Security Bit | — | Yes (design protection) |
| Tape and Reel | — | Yes (suffix T) |