EP910PC-15 vs EP910PC-15T Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-15 sa pamamagitan ng Altera at EP910PC-15T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910PC-15 EP910PC-15T
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Altera Classic EPLD Altera Classic EPLD
Usable Gates 900 —
Macrocells 24 —
Maximum Pin-to-Pin Delay (tpd) 15 ns —
Counter Frequency (fCNT) 100 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (nominal)
Supply Current (Icc) 80 mA typical —
Dedicated Inputs 10 —
Dedicated I/O Pins 12 —
Temperature na Operasyon 0C to +70C (commercial) 0C to +70C (commercial)
Packhaging 24-pin PDIP (PDIP-24, 0.300 inch) 40-pin PDIP (Plastic DIP)
Uri ng Pagpapasok Through-Hole Through-hole (DIP)
Process Technology CMOS, UV-erasable —
Programming Method Altera Logic Programmer card JEDEC fuse map via Altera LogicMap / MAX+PLUS II
Tindminan RoHS [DATA_NEEDED: RoHS status - EP910 is a legacy through-hole part, likely non-RoHS] [DATA_NEEDED: RoHS compliance status]
Level ng MSL Not applicable (through-hole) —
Product Type — EPLD (Erasable Programmable Logic Device)
Macrocell Count — 24
Dedicated Input Pins — 10
Pin-to-Pin Delay (tPD) — 15 ns
Speed Grade — -15 (15 ns)
Technology — CMOS, UV-erasable / OTP
Output Drive Current — [DATA_NEEDED: IOL per output]
Logic Capacity — 24 macrocells / 72 product terms (typical Classic architecture)
Lead-Free — [DATA_NEEDED: lead-free status]
Security Bit — Yes (design protection)
Tape and Reel — Yes (suffix T)

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