EP910PC-15 vs EP910PC-15T 比較
詳細並排比較 EP910PC-15 由 Altera 與 EP910PC-15T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PC-15 | EP910PC-15T |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Usable Gates | 900 | — |
| Macrocells | 24 | — |
| Maximum Pin-to-Pin Delay (tpd) | 15 ns | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (nominal) |
| Supply Current (Icc) | 80 mA typical | — |
| Dedicated Inputs | 10 | — |
| Dedicated I/O Pins | 12 | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| 封裝 | 24-pin PDIP (PDIP-24, 0.300 inch) | 40-pin PDIP (Plastic DIP) |
| 安裝類型 | Through-Hole | Through-hole (DIP) |
| Process Technology | CMOS, UV-erasable | — |
| Programming Method | Altera Logic Programmer card | JEDEC fuse map via Altera LogicMap / MAX+PLUS II |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - EP910 is a legacy through-hole part, likely non-RoHS] | [DATA_NEEDED: RoHS compliance status] |
| MSL 等級 | Not applicable (through-hole) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | — | 24 |
| Dedicated Input Pins | — | 10 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Speed Grade | — | -15 (15 ns) |
| Technology | — | CMOS, UV-erasable / OTP |
| Output Drive Current | — | [DATA_NEEDED: IOL per output] |
| Logic Capacity | — | 24 macrocells / 72 product terms (typical Classic architecture) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Security Bit | — | Yes (design protection) |
| Tape and Reel | — | Yes (suffix T) |