EPM5128LC-1 vs EPM5128JC-2 तुलना
विस्तृत दोनों ओर की तुलना EPM5128LC-1 द्वारा Altera और EPM5128JC-2 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPM5128LC-1 | EPM5128JC-2 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Logic Elements / Macrocells | 128 macrocells | — |
| Number of Usable Gates | [DATA_NEEDED: usable gates] | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 52 | — |
| Total User I/O | 60 (max) | — |
| Propagation Delay (tpd) | 30 ns | — |
| Supply Voltage (VCC) | 5 V (±10%) | — |
| Process Technology | CMOS EPROM, UV-erasable | CMOS |
| Programmability | UV-erasable / OTP (windowed package) | — |
| Package Type | 68-pin J-lead ceramic chip carrier (PLCC windowed) | — |
| ऑपरेटिंग तापमान | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| माउंटिंग प्रकार | Surface Mount (J-lead PLCC socket compatible) | Surface Mount |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic windowed package contains lead-bearing solder) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | UV-Erasable Programmable Logic Device (PLD) |
| Macrocells | — | 128 |
| Propagation Delay (tPD) | — | 45 ns (max) |
| Maximum Counter Frequency (fCNT) | — | 50 MHz |
| Input Setup Time (tSU) | — | 7.5 ns |
| Output Drive Current (IOH/IOL) | — | 12 mA DC |
| पैकेज | — | 68-pin CQCC (Ceramic Quad Flat Pack), windowed |
| सप्लाई वोल्टेज | — | 5 V (nominal) |
| Program/Erase Method | — | UV (ceramic window) |
| Erase/Program Cycles | — | [DATA_NEEDED: minimum erase/program cycles] |
| Logic Family | — | TTL-compatible I/O |