EPM5128LC-1 vs EPM5128JC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128LC-1 sa pamamagitan ng Altera at EPM5128JC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5128LC-1 EPM5128JC-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Logic Elements / Macrocells 128 macrocells —
Number of Usable Gates [DATA_NEEDED: usable gates] —
Dedicated Inputs 7 7
Bidirectional I/O Pins 52 —
Total User I/O 60 (max) —
Propagation Delay (tpd) 30 ns —
Supply Voltage (VCC) 5 V (±10%) —
Process Technology CMOS EPROM, UV-erasable CMOS
Programmability UV-erasable / OTP (windowed package) —
Package Type 68-pin J-lead ceramic chip carrier (PLCC windowed) —
Temperature na Operasyon 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
JTAG Support IEEE 1149.1 boundary-scan —
Uri ng Pagpapasok Surface Mount (J-lead PLCC socket compatible) Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS status] Non-compliant (ceramic windowed package contains lead-bearing solder)
Lead-Free [DATA_NEEDED: lead-free status] —
Device Type — UV-Erasable Programmable Logic Device (PLD)
Macrocells — 128
Propagation Delay (tPD) — 45 ns (max)
Maximum Counter Frequency (fCNT) — 50 MHz
Input Setup Time (tSU) — 7.5 ns
Output Drive Current (IOH/IOL) — 12 mA DC
Packhaging — 68-pin CQCC (Ceramic Quad Flat Pack), windowed
Volte ng Pagbibigay — 5 V (nominal)
Program/Erase Method — UV (ceramic window)
Erase/Program Cycles — [DATA_NEEDED: minimum erase/program cycles]
Logic Family — TTL-compatible I/O

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