EP1810GI-45 vs EP1810JI-35 Perbandingan
Perbandingan bersamaan detil EP1810GI-45 dari Altera dan EP1810JI-35 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP1810GI-45 | EP1810JI-35 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 48 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Speed Grade | -45 | -35 |
| Technology | CMOS | — |
| Package Type | Ceramic Pin Grid Array with UV window | — |
| Jumlah Pin | 68 | — |
| Tipe Mounting | Through-Hole | Through-Hole (J-lead) |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| Status RoHS | Non-compliant (ceramic PGA) | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Lead-Free | No | — |
| Suhu Kerja | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| Tegangan Pemuat | [DATA_NEEDED: VCC range] | 5 V (typical classic EPLD) |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Paket | — | 28-pin JLCC (J-leaded ceramic, windowed) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Level MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |