EP1810GI-45 vs EP1810JI-35 比較
詳細並排比較 EP1810GI-45 由 Altera 與 EP1810JI-35 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810GI-45 | EP1810JI-35 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 48 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Speed Grade | -45 | -35 |
| Technology | CMOS | — |
| Package Type | Ceramic Pin Grid Array with UV window | — |
| 腳位數 | 68 | — |
| 安裝類型 | Through-Hole | Through-Hole (J-lead) |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| RoHS 狀態 | Non-compliant (ceramic PGA) | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Lead-Free | No | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| 供應電壓 | [DATA_NEEDED: VCC range] | 5 V (typical classic EPLD) |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| 封裝 | — | 28-pin JLCC (J-leaded ceramic, windowed) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |