EP1810GI-45 vs EP1810JI-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GI-45 sa pamamagitan ng Altera at EP1810JI-35 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810GI-45 | EP1810JI-35 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 48 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Speed Grade | -45 | -35 |
| Technology | CMOS | — |
| Package Type | Ceramic Pin Grid Array with UV window | — |
| Bilang ng Pin | 68 | — |
| Uri ng Pagpapasok | Through-Hole | Through-Hole (J-lead) |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| Tindminan RoHS | Non-compliant (ceramic PGA) | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Lead-Free | No | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC range] | 5 V (typical classic EPLD) |
| Device Family | — | Classic EPLD |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Packhaging | — | 28-pin JLCC (J-leaded ceramic, windowed) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |