EP1810LC-25 vs EP1810LI-35 Perbandingan

Perbandingan bersamaan detil EP1810LC-25 dari Altera dan EP1810LI-35 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP1810LC-25 EP1810LI-35
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Product Family Altera Classic EPLD —
Part Number EP1810LC-25 —
Macrocells 48 48
Propagation Delay (tPD) 25 ns 35 ns
Dedicated Inputs 12 —
I/O Pins 48 —
External Clock Inputs 4 —
Supply Voltage (VCC) 5 V (TTL-compatible) —
Operating Mode Turbo-only (no slow-power mode) —
Paket 68-pin JLCC (J-leaded ceramic chip carrier) 68-pin PLCC (J-Lead, plastic)
Package Code LC = 68-pin JLCC —
Tipe Mounting Surface Mount Surface Mount (PLCC socket compatible)
Technology CMOS EPLD (erasable programmable logic device) CMOS, UV-erasable EPROM configuration cell
Programmable Interconnect Global + Local buses —
Programming Method Altera Classic programmer + MAX+PLUS II legacy flow —
Status Lingkungan Hidup Obsolete (legacy Altera Classic family) —
Status RoHS [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] [DATA_NEEDED: RoHS compliance status]
Suhu Kerja [DATA_NEEDED: temperature grade for LC package] -40 C to +85 C (industrial, 'I' suffix)
Manufacturer — Rochester Electronics, LLC (original Altera design)
Part Family — Altera Classic EPLD
Device Type — Erasable Programmable Logic Device (EPLD)
Speed Grade — 35 (slowest in EP1810L family)
Pin/Package Code — PLCC-68 / PQCC68
Tegangan Pemuat — 5 V (TTL-compatible I/O)
JTAG Boundary Scan — IEEE 1149.1 compliant
Logic Elements — Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA)
Lead-Free — [DATA_NEEDED: lead-free status]
Level MSL — [DATA_NEEDED: MSL rating]

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