EP1810LC-25 vs EP1810LI-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-25 sa pamamagitan ng Altera at EP1810LI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810LC-25 | EP1810LI-35 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Family | Altera Classic EPLD | — |
| Part Number | EP1810LC-25 | — |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | 35 ns |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 5 V (TTL-compatible) | — |
| Operating Mode | Turbo-only (no slow-power mode) | — |
| Packhaging | 68-pin JLCC (J-leaded ceramic chip carrier) | 68-pin PLCC (J-Lead, plastic) |
| Package Code | LC = 68-pin JLCC | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (PLCC socket compatible) |
| Technology | CMOS EPLD (erasable programmable logic device) | CMOS, UV-erasable EPROM configuration cell |
| Programmable Interconnect | Global + Local buses | — |
| Programming Method | Altera Classic programmer + MAX+PLUS II legacy flow | — |
| Katayuan ng Lifecycle | Obsolete (legacy Altera Classic family) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] | [DATA_NEEDED: RoHS compliance status] |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade for LC package] | -40 C to +85 C (industrial, 'I' suffix) |
| Manufacturer | — | Rochester Electronics, LLC (original Altera design) |
| Part Family | — | Altera Classic EPLD |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Speed Grade | — | 35 (slowest in EP1810L family) |
| Pin/Package Code | — | PLCC-68 / PQCC68 |
| Volte ng Pagbibigay | — | 5 V (TTL-compatible I/O) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Logic Elements | — | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |