EP1810LC-45 vs EP1810LC-25 Perbandingan

Perbandingan bersamaan detil EP1810LC-45 dari Rochester Electronics dan EP1810LC-25 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP1810LC-45 EP1810LC-25
Merek Rochester Electronics Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family Altera Classic EPLD —
Device Type EPLD (Erasable Programmable Logic Device) —
Usable Gates 900 —
Macro Cells 48 —
Maximum Inputs 64 —
Maximum Outputs 48 —
Logic Array Blocks 4 —
Propagation Delay (tpd) 45 ns —
Maximum Operating Frequency 22.2 MHz —
Supply Voltage (Vcc) 5 V (±5%) —
Process Technology 5 V CMOS EPROM —
Paket 68-pin PLCC (J-lead) 68-pin JLCC (J-leaded ceramic chip carrier)
Suhu Kerja 0 °C to +70 °C (commercial) [DATA_NEEDED: temperature grade for LC package]
Tipe Mounting Surface Mount (PLCC socket compatible) Surface Mount
Status RoHS [DATA_NEEDED: RoHS status of Rochester-sourced part] [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
Lead-Free [DATA_NEEDED: lead-free finish] —
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
Macrocells — 48
Propagation Delay (tPD) — 25 ns
Dedicated Inputs — 12
I/O Pins — 48
External Clock Inputs — 4
Supply Voltage (VCC) — 5 V (TTL-compatible)
Operating Mode — Turbo-only (no slow-power mode)
Package Code — LC = 68-pin JLCC
Technology — CMOS EPLD (erasable programmable logic device)
Programmable Interconnect — Global + Local buses
Programming Method — Altera Classic programmer + MAX+PLUS II legacy flow
Status Lingkungan Hidup — Obsolete (legacy Altera Classic family)

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