EP1810LC-45 vs EP1810LC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-45 sa pamamagitan ng Rochester Electronics at EP1810LC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810LC-45 EP1810LC-25
Brand Rochester Electronics Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Altera Classic EPLD —
Device Type EPLD (Erasable Programmable Logic Device) —
Usable Gates 900 —
Macro Cells 48 —
Maximum Inputs 64 —
Maximum Outputs 48 —
Logic Array Blocks 4 —
Propagation Delay (tpd) 45 ns —
Maximum Operating Frequency 22.2 MHz —
Supply Voltage (Vcc) 5 V (±5%) —
Process Technology 5 V CMOS EPROM —
Packhaging 68-pin PLCC (J-lead) 68-pin JLCC (J-leaded ceramic chip carrier)
Temperature na Operasyon 0 °C to +70 °C (commercial) [DATA_NEEDED: temperature grade for LC package]
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS status of Rochester-sourced part] [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
Lead-Free [DATA_NEEDED: lead-free finish] —
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
Macrocells — 48
Propagation Delay (tPD) — 25 ns
Dedicated Inputs — 12
I/O Pins — 48
External Clock Inputs — 4
Supply Voltage (VCC) — 5 V (TTL-compatible)
Operating Mode — Turbo-only (no slow-power mode)
Package Code — LC = 68-pin JLCC
Technology — CMOS EPLD (erasable programmable logic device)
Programmable Interconnect — Global + Local buses
Programming Method — Altera Classic programmer + MAX+PLUS II legacy flow
Katayuan ng Lifecycle — Obsolete (legacy Altera Classic family)

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