EP1SGX25FG1020C4 vs EP1SGX25FG672C7 Perbandingan

Perbandingan bersamaan detil EP1SGX25FG1020C4 dari Altera dan EP1SGX25FG672C7 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP1SGX25FG1020C4 EP1SGX25FG672C7
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family Stratix GX Stratix GX
Logic Elements 25,560 LE —
Embedded Memory 1,920 Kbits —
Total RAM Blocks M-RAM + M4K blocks (per Stratix GX architecture) —
DSP Blocks 10 (DSP blocks) —
Maximum User I/O Pins [DATA_NEEDED: exact pin count from datasheet] —
Embedded Transceivers 4 channels Yes (multi-gigabit, up to 3.125 Gbps)
Transceiver Data Rate 600 Mbps to 3.125 Gbps —
Core Voltage 1.5 V (typical) 1.5 V
Paket 1020-pin FineLine BGA (FBGA), 1.27 mm pitch 672-pin FineLine BGA (FG672)
Suhu Kerja 0 °C to +85 °C (commercial) 0C to +85C (commercial, speed grade C7)
Speed Grade C4 7 (commercial)
Configuration Modes PS, PPS, PPA, JTAG —
Process Technology 0.13 µm CMOS, SRAM-based 0.13 micron
Configuration Device Required Yes — external (EPC16 / EPCS recommended) —
Status Lingkungan Hidup Obsolete / Last-time-buy from authorized distributors Obsolete (per Altera/Intel product discontinuance notices)
Status RoHS [DATA_NEEDED: confirm via manufacturer product page] [DATA_NEEDED: RoHS compliance]
Series — Stratix
Logic Elements (LE) — 25,660
Total RAM Bits — 1,944,576 bits
User I/O Pins — 455
Number of Transceivers — [DATA_NEEDED: exact transceiver count]
PLLs — 4
Global Clocks — 16
Tipe Mounting — Surface Mount
Configuration Method — SRAM-based, JTAG/AS/PS supported

Spek dan Sumber

Buka Semua Produk Buat BOM Ajukan Diskon