EP1SGX25FG1020C4 vs EP1SGX25FG672C7 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1SGX25FG1020C4 disebabkan oleh Altera dan EP1SGX25FG672C7 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP1SGX25FG1020C4 EP1SGX25FG672C7
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family Stratix GX Stratix GX
Logic Elements 25,560 LE —
Embedded Memory 1,920 Kbits —
Total RAM Blocks M-RAM + M4K blocks (per Stratix GX architecture) —
DSP Blocks 10 (DSP blocks) —
Maximum User I/O Pins [DATA_NEEDED: exact pin count from datasheet] —
Embedded Transceivers 4 channels Yes (multi-gigabit, up to 3.125 Gbps)
Transceiver Data Rate 600 Mbps to 3.125 Gbps —
Core Voltage 1.5 V (typical) 1.5 V
Kemasan 1020-pin FineLine BGA (FBGA), 1.27 mm pitch 672-pin FineLine BGA (FG672)
Suhu Operasi 0 °C to +85 °C (commercial) 0C to +85C (commercial, speed grade C7)
Speed Grade C4 7 (commercial)
Configuration Modes PS, PPS, PPA, JTAG —
Process Technology 0.13 µm CMOS, SRAM-based 0.13 micron
Configuration Device Required Yes — external (EPC16 / EPCS recommended) —
Status Lingkungan Hidup Obsolete / Last-time-buy from authorized distributors Obsolete (per Altera/Intel product discontinuance notices)
Status RoHS [DATA_NEEDED: confirm via manufacturer product page] [DATA_NEEDED: RoHS compliance]
Series — Stratix
Logic Elements (LE) — 25,660
Total RAM Bits — 1,944,576 bits
User I/O Pins — 455
Number of Transceivers — [DATA_NEEDED: exact transceiver count]
PLLs — 4
Global Clocks — 16
Jenis Pemasangan — Surface Mount
Configuration Method — SRAM-based, JTAG/AS/PS supported

Laporan Datasheet & Sumber

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