EP3SE50F484I4LN vs EP3SE50F484I4N Perbandingan

Perbandingan bersamaan detil EP3SE50F484I4LN dari Intel dan EP3SE50F484I4N dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP3SE50F484I4LN EP3SE50F484I4N
Merek Intel Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Family Stratix III E —
Logic Elements (LE) 47,500 47,500
Logic Array Blocks (LABs) 1,900 1,900
Embedded Memory 5.76 Mbit (estimated from 47.5K LE family) —
User I/O Count 296 —
Process Node 65 nm —
Core Voltage (VCCINT) 0.9 V —
Auxiliary Voltage (VCCAUX) 1.1 V —
I/O Voltage (VCCIO) 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.0 V (bank-dependent) —
Paket 484-ball FBGA (FineLine BGA) 484-ball FC-FBGA (F484)
Pin/Pitch 484 balls, 1.0 mm pitch —
Suhu Kerja -40C to +100C (industrial I4 grade) 0 C to +85 C (Industrial)
Configuration SRAM-based (external flash/EPCS required) —
Status RoHS Compliant (LN suffix indicates lead-free) —
Lead-Free Yes (LF / N suffix indicates lead-free) —
Transceivers 0 (F484 package does not include transceiver banks) —
PLL Count Up to 12 (estimated for Stratix III E family) —
DSP Blocks (18x18 Multipliers) [DATA_NEEDED: DSP block count] —
Design Tool Quartus II (legacy, support via Altera/Intel subscription) —
Device Family — Stratix III E
Adaptive Logic Modules (ALMs) — 19,000
Embedded Memory (TriMatrix) — 2,136 Kbits
Embedded Multipliers (18x18) — 384
User I/Os — 296
I/O Banks — 12
PLLs — 8
Global Clock Networks — 16
Maximum User I/O Frequency — 800 MHz (per DigChip datasheet summary)
Process Technology — 65 nm CMOS
Core Voltage — 1.1 V
Speed Grade — I4
Lead-Free / RoHS — Lead-free (per ampheo listing)

Spek dan Sumber

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