EP910LC-35H vs EP910DC-35 Perbandingan

Perbandingan bersamaan detil EP910LC-35H dari Altera dan EP910DC-35 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP910LC-35H EP910DC-35
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family Classic EPLD (EP910) Classic EPLD EP910
Logic Elements 24 macrocells —
Equivalent Gates 450 usable gates —
Propagation Delay (tpd) 35 ns 35 ns
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM cell
Paket 40-pin Ceramic DIP (H suffix) 40-pin CDIP (Ceramic DIP) with quartz window
User I/O Pins 36 —
Dedicated Inputs 10 12
Suhu Kerja [DATA_NEEDED: operating temperature range grade] 0 °C to +70 °C (commercial)
Erasure Method UV (quartz window on H package) —
Programming Method Altera hardware programmer JEDEC fuse map via device programmer; UV erase
Logic Levels TTL compatible —
Arus Memerintah [DATA_NEEDED: typical ICC value] —
Process Node [DATA_NEEDED: process geometry] —
Tipe Mounting Through-hole (Ceramic DIP) —
Status RoHS unknown Non-compliant (ceramic DIP with Pb-bearing lead finish)
Lifecycle Obsolete (long-term supply via Rochester Electronics) Obsolete / last-time-buy from authorized distributors
Device Type — UV-Erasable CMOS PLD (PAL-type)
Architecture — PAL-type sum-of-products AND-OR array
Usable Gates — 900 gates
Macrocells — 24
Product Terms — 240
I/O Pins — 24
Total Inputs — 36
Frekuensi Bawah Maximum — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole

Spek dan Sumber

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