EP910LC-35H vs EP910DC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-35H sa pamamagitan ng Altera at EP910DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910LC-35H EP910DC-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Classic EPLD (EP910) Classic EPLD EP910
Logic Elements 24 macrocells —
Equivalent Gates 450 usable gates —
Propagation Delay (tpd) 35 ns 35 ns
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM cell
Packhaging 40-pin Ceramic DIP (H suffix) 40-pin CDIP (Ceramic DIP) with quartz window
User I/O Pins 36 —
Dedicated Inputs 10 12
Temperature na Operasyon [DATA_NEEDED: operating temperature range grade] 0 °C to +70 °C (commercial)
Erasure Method UV (quartz window on H package) —
Programming Method Altera hardware programmer JEDEC fuse map via device programmer; UV erase
Logic Levels TTL compatible —
Kuru-kuryente ng Kapayapaan [DATA_NEEDED: typical ICC value] —
Process Node [DATA_NEEDED: process geometry] —
Uri ng Pagpapasok Through-hole (Ceramic DIP) —
Tindminan RoHS unknown Non-compliant (ceramic DIP with Pb-bearing lead finish)
Lifecycle Obsolete (long-term supply via Rochester Electronics) Obsolete / last-time-buy from authorized distributors
Device Type — UV-Erasable CMOS PLD (PAL-type)
Architecture — PAL-type sum-of-products AND-OR array
Usable Gates — 900 gates
Macrocells — 24
Product Terms — 240
I/O Pins — 24
Total Inputs — 36
Maksimum na Taktiko ng Oras — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole

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