EPM5192-1LC vs EPM5192AGC Perbandingan

Perbandingan bersamaan detil EPM5192-1LC dari Altera dan EPM5192AGC dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM5192-1LC EPM5192AGC
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 5000 MAX 5000 (High-Speed, High-Density MAX 5000 Devices)
Device Type CPLD (Complex Programmable Logic Device) UV-Erasable / OTP Complex PLD (EPLD)
Usable Gates 3,750 —
Macrocells 192 192
Logic Array Blocks (LABs) 4 —
User I/O Pins 64 —
Maximum Operating Frequency 62.5 MHz —
Propagation Delay (tpd) [DATA_NEEDED: -1 speed grade tpd in ns] —
Tegangan Pemuat 5 V [DATA_NEEDED: VCC nominal and tolerance]
Process Technology UV EPROM, erasable windowless CMOS
Programmable Interconnect PIA (Programmable Interconnect Array) —
JTAG Boundary Scan IEEE 1149.1 compliant —
Paket 64-pin Ceramic J-Lead Chip Carrier (LC) 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless)
Tipe Mounting Surface Mount Through-hole (Pin Grid Array)
Suhu Kerja 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
Status RoHS Non-compliant (ceramic windowless package, lead-bearing termination) Non-compliant (ceramic PGA contains lead; legacy military/industrial grade)
Logic Density — High-density (per MAX 5000 family definition)
Architecture — CMOS, sum-of-products with macrocell output logic
Speed Grade Suffix — C (commercial grade; specific pin-to-pin delay varies by base number -15/-20)
Programmability — UV-erasable (windowed package) / One-Time-Programmable (windowless variant)
Security Bit — Programmable security bit (per MAX 5000 family)
Lifecycle — Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs)
Programming Support — MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers

Spek dan Sumber

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