EPM7128SQC100-15 vs EPM7128STC100-10 Perbandingan

Perbandingan bersamaan detil EPM7128SQC100-15 dari Altera dan EPM7128STC100-10 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Altera
EPM7128SQC100-15 EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 ⚠ Waktu Beli Terakhir

Perbandingan Spesifikasi

Parameter Umum EPM7128SQC100-15 EPM7128STC100-10
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Waktu Pembelian Terakhir Obsolete
Harga Unit (USD) $8,20 —
Family MAX 7000 MAX 7000S
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 128 —
Logic Array Blocks (LABs) 4 (16 macrocells each) —
User I/Os 84 84
Pin-to-Pin Delay (tPD) 15 ns —
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX value] —
Typical Gate Count 2,500 gates —
Supply Voltage (VCCINT) 5 V (5% tolerance) 5 V
Programming Technology EEPROM (in-system programmable via JTAG) —
JTAG Interface IEEE Std. 1149.1 compliant —
Paket 100-pin PQFP (Plastic Quad Flat Pack) TQFP-100 (C100)
Suhu Kerja 0C to +70C (Commercial) 0C to +70C (commercial)
Tipe Mounting Surface Mount Surface Mount
Level MSL 3 (168 hours) —
Status RoHS Non-compliant (SnPb lead finish - legacy PQFP) [DATA_NEEDED: RoHS compliance status not in provided data]
Macro Cells — 128
Usable Gates — 2,500
Logic Array Blocks — 8 (16 macrocells per LAB)
Propagation Delay (tPD) — 10 ns
Internal Counter Frequency (fCNT) — 100 MHz
Logic Family — CMOS
MultiVolt I/O Voltage — 3.3 V / 5 V
Jumlah Pin — 100
Programmability — In-System Programmable (JTAG, IEEE 1149.1), EEPROM

Spek dan Sumber

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