EPM7128SQC100-15 vs EPM7128STC100-10 比較
詳細並排比較 EPM7128SQC100-15 由 Altera 與 EPM7128STC100-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 Obsolete規格比較
| 參數 | EPM7128SQC100-15 | EPM7128STC100-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| 單價 (USD) | $8.20 | — |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 4 (16 macrocells each) | — |
| User I/Os | 84 | 84 |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX value] | — |
| Typical Gate Count | 2,500 gates | — |
| Supply Voltage (VCCINT) | 5 V (5% tolerance) | 5 V |
| Programming Technology | EEPROM (in-system programmable via JTAG) | — |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| 封裝 | 100-pin PQFP (Plastic Quad Flat Pack) | TQFP-100 (C100) |
| 工作溫度 | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| 安裝類型 | Surface Mount | Surface Mount |
| MSL 等級 | 3 (168 hours) | — |
| RoHS 狀態 | Non-compliant (SnPb lead finish - legacy PQFP) | [DATA_NEEDED: RoHS compliance status not in provided data] |
| Macro Cells | — | 128 |
| Usable Gates | — | 2,500 |
| Logic Array Blocks | — | 8 (16 macrocells per LAB) |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family | — | CMOS |
| MultiVolt I/O Voltage | — | 3.3 V / 5 V |
| 腳位數 | — | 100 |
| Programmability | — | In-System Programmable (JTAG, IEEE 1149.1), EEPROM |