EPM9320LI84-20N vs EPM9320LC84-15 Perbandingan

Perbandingan bersamaan detil EPM9320LI84-20N dari Altera dan EPM9320LC84-15 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM9320LI84-20N EPM9320LC84-15
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 320 320
Usable Gates 6,000 to 12,000 6,000
User I/O Pins 60 —
Total Pins 84 —
Paket PLCC-84 (Plastic Leaded Chip Carrier, J-lead) 84-pin PLCC (Plastic Leaded Chip Carrier)
Propagation Delay (tPD) 20 ns (speed grade -20) 15 ns (max)
Pin-to-Pin Delay 16 ns (per DigChip spec block) —
Maximum Counter Frequency 118 MHz —
Logic Family CMOS, EEPROM-based —
Tegangan Pemuat 5.0 V —
Suhu Kerja 0 C to +70 C (commercial) -40C to +85C (commercial) [DATA_NEEDED: exact grade]
Programming Interface IEEE 1149.1 JTAG, in-system programmable —
Architecture Multiple Array MatriX (MAX) - third generation —
Process Technology Advanced CMOS EEPROM —
Status RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: confirm from manufacturer]
Series — EPM9320
Logic Array Blocks (LABs) — 20
Frekuensi Bawah Maximum — 117.6 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (5.0 V nominal)
Programmability — 5.0 V in-system programmable (ISP) via JTAG
JTAG Interface — IEEE Std. 1149.1 boundary-scan compliant
Tipe Mounting — Surface Mount
Technology — CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX)
Built-in Pull-up Resistors — Yes, on every I/O pin
Architecture Feature — Pin-locking across design iterations

Spek dan Sumber

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