EPM9320LI84-20N vs EPM9320LC84-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320LI84-20N sa pamamagitan ng Altera at EPM9320LC84-15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320LI84-20N | EPM9320LC84-15 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 to 12,000 | 6,000 |
| User I/O Pins | 60 | — |
| Total Pins | 84 | — |
| Packhaging | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | 15 ns (max) |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) | — |
| Maximum Counter Frequency | 118 MHz | — |
| Logic Family | CMOS, EEPROM-based | — |
| Volte ng Pagbibigay | 5.0 V | — |
| Temperature na Operasyon | 0 C to +70 C (commercial) | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| Process Technology | Advanced CMOS EEPROM | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: confirm from manufacturer] |
| Series | — | EPM9320 |
| Logic Array Blocks (LABs) | — | 20 |
| Maksimum na Taktiko ng Oras | — | 117.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Uri ng Pagpapasok | — | Surface Mount |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |