EPF6016QI208-3N - FLEX 6000 FPGA 16K Gates 171 I/O 208-PQFP | Intel
MPN: EPF6016QI208-3N ✗ Akhir HidupEPF6016QI208-3N Ringkasan
An FPGA (Field Programmable Gate Array) is a programmable integrated circuit that combines configurable logic blocks, programmable interconnect, and I/O cells on a single die. The FLEX 6000 family specifically targets low-cost, high-volume designs as an alternative to gate arrays, allowing rapid design changes during prototyping without NRE charges. FPGAs sit in the programmable-logic hierarchy alongside CPLDs and serve as the highest-density programmable logic option for logic integration, glue logic, and pre-ASIC prototyping.
Key features include 1,320 logic elements distributed across 132 LABs, 171 user I/Os, an internal frequency up to 125 MHz, on-chip SRAM configuration memory, JTAG-based IEEE 1149.1 boundary-scan testing support, and multi-voltage I/O support. The 'QI' package designator denotes the industrial temperature grade and PQFP form factor, while the '-3' speed grade and 'N' lead-free suffix indicate lead-free / RoHS-compliant termination. The 208-pin PQFP (BFQFP) is a low-profile gull-wing surface-mount package suitable for socketed or hand-soldered designs.
Architecturally, the FLEX 6000 device uses a continuous-channel interconnect with shared fast-track lines between LABs and adjacent LAB-row fast lines. Each LAB contains 10 Logic Elements, each comprising a 4-input look-up table (LUT), a programmable register, and carry-chain logic for arithmetic functions. Configuration is loaded from an external EPROM or serial configuration device at power-up via the FLEX 6000's dedicated configuration interface.
Typical applications include legacy bus-bridge and interface adaptation in industrial controllers, communication protocol bridging (UART/SPI/I2C consolidation), pre-ASIC prototyping, ASIC prototyping, machine-control state machines, glue-logic replacement for discrete TTL, and educational logic-design platforms. The 5 V tolerance and PQFP form factor make it especially suited to retrofit projects targeting older 5 V backplanes.
When designing with this FPGA, ensure that the configuration EPROM (EPC1, EPC2, or compatible serial configuration device) is correctly sized and that JTAG chain integrity is validated. Watch for 5 V I/O-bank compatibility - the FLEX 6000 supports mixed-voltage I/O, but each bank must be powered from a single rail. Use Quartus II MAX+PLUS II legacy software for design entry, as modern Quartus Prime flows do not support the FLEX 6000 family.
Alternatif penggantian untuk EPF6016QI208-3N — paket yang sama, pin-pada-pin kompatibel. Bagian paket yang berbeda memerlukan kerja ulang PCB diabaikan.
Variasi di dalam seri ini
Model-series yang sama yang kompatibel dengan penggantian EPF6016QI208-3N (sama faktor bentuk dan footprint) — berbeda di dalam Operating Temperature, Package, Process Technology, RoHS Status, Speed Grade.
EPF6016QI208-3
✅ Drop-InKontak untuk harga
Lihat Datasheet →EPF6016QC208-3N
✅ Drop-InKontak untuk harga
Lihat Datasheet →EPF6016QC208-3
✅ Drop-InKontak untuk harga
Lihat Datasheet →EPF6016AQC208-3N
✅ Drop-InKontak untuk harga
Lihat Datasheet →EPF6016AQC208-3
✅ Drop-InKontak untuk harga
Lihat Datasheet →EPF6016AQC208-2N
✅ Drop-InKontak untuk harga
Lihat Datasheet →EPF6016QI208-3N Rating Maksimal & Karakteristik Listrik
| Family | FLEX 6000 |
| Device Type | FPGA - Field Programmable Gate Array |
| Usable Gates | 16,000 |
| Logic Elements (LEs) | 1,320 |
| Logic Array Blocks (LABs) | 132 |
| User I/Os | 171 |
| Maximum Internal Frequency | 125 MHz |
| Technology Node | 0.42 µm CMOS |
| Core Supply Voltage | 5 V |
| Suhu Kerja | 0C to +85C (Industrial) |
| Paket | 208-BFQFP / 208-PQFP |
| Package Code | PQFP, FQFP |
| Terminal Form | Gull Wing |
| Configuration | SRAM (external serial config device) |
| JTAG / Boundary Scan | IEEE 1149.1 compliant |
| Status RoHS | Lead-free (N suffix) / RoHS compliant |
| Speed Grade | -3 |
Konfigurasi Pin EPF6016QI208-3N
| Pin produk 1 | I/O — User I/O (bank 1) |
| Pin produk 2 | I/O — User I/O (bank 1) |
| Pin produk 3 | I/O — User I/O (bank 1) |
| Pin produk 4 | I/O — User I/O (bank 1) |
| Pin produk 5 | I/O — User I/O (bank 1) |
| Pin produk 6 | I/O — User I/O (bank 1) |
| Pin produk 7 | I/O — User I/O (bank 1) |
| Pin produk 8 | I/O — User I/O (bank 1) |
| Pin produk 9 | I/O — User I/O (bank 1) |
| Pin produk 10 | I/O — User I/O (bank 1) |
| Pin produk 11 | VCCINT — Core supply voltage (5V) |
| Pin produk 12 | I/O — User I/O (bank 1) |
| Pin produk 13 | I/O — User I/O (bank 1) |
| Pin produk 14 | I/O — User I/O (bank 1) |
| Pin produk 15 | I/O — User I/O (bank 1) |
| Pin produk 16 | I/O — User I/O (bank 1) |
| Pin produk 17 | I/O — User I/O (bank 1) |
| Pin produk 18 | I/O — User I/O (bank 1) |
| Pin produk 19 | I/O — User I/O (bank 1) |
| Pin produk 20 | I/O — User I/O (bank 1) |
| Pin produk 21 | I/O — User I/O (bank 1) |
| Pin produk 22 | I/O — User I/O (bank 1) |
| Pin produk 23 | GND — Ground |
| Pin produk 24 | I/O — User I/O (bank 2) |
| Pin produk 25 | I/O — User I/O (bank 2) |
| Pin produk 26 | I/O — User I/O (bank 2) |
| Pin produk 27 | I/O — User I/O (bank 2) |
| Pin produk 28 | I/O — User I/O (bank 2) |
| Pin produk 29 | I/O — User I/O (bank 2) |
| Pin produk 30 | I/O — User I/O (bank 2) |
| Pin produk 31 | I/O — User I/O (bank 2) |
| Pin produk 32 | I/O — User I/O (bank 2) |
| Pin produk 33 | I/O — User I/O (bank 2) |
| Pin produk 34 | I/O — User I/O (bank 2) |
| Pin produk 35 | I/O — User I/O (bank 2) |
| Pin produk 36 | I/O — User I/O (bank 2) |
| Pin produk 37 | VCCIO2 — I/O bank 2 supply voltage |
| Pin produk 38 | I/O — User I/O (bank 2) |
| Pin produk 39 | I/O — User I/O (bank 2) |
| Pin produk 40 | I/O — User I/O (bank 2) |
| Pin produk 41 | I/O — User I/O (bank 2) |
| Pin produk 42 | I/O — User I/O (bank 2) |
| Pin produk 43 | I/O — User I/O (bank 2) |
| Pin produk 44 | I/O — User I/O (bank 2) |
| Pin produk 45 | I/O — User I/O (bank 2) |
| Pin produk 46 | I/O — User I/O (bank 2) |
| Pin produk 47 | I/O — User I/O (bank 2) |
| Pin produk 48 | GND — Ground |
| Pin produk 49 | I/O — User I/O (bank 3) |
| Pin produk 50 | I/O — User I/O (bank 3) |
| Pin produk 51 | I/O — User I/O (bank 3) |
| Pin produk 52 | I/O — User I/O (bank 3) |
| Pin produk 53 | I/O — User I/O (bank 3) |
| Pin produk 54 | I/O — User I/O (bank 3) |
| Pin produk 55 | I/O — User I/O (bank 3) |
| Pin produk 56 | I/O — User I/O (bank 3) |
| Pin produk 57 | I/O — User I/O (bank 3) |
| Pin produk 58 | I/O — User I/O (bank 3) |
| Pin produk 59 | I/O — User I/O (bank 3) |
| Pin produk 60 | I/O — User I/O (bank 3) |
| Pin produk 61 | VCCIO3 — I/O bank 3 supply voltage |
| Pin produk 62 | I/O — User I/O (bank 3) |
| Pin produk 63 | I/O — User I/O (bank 3) |
| Pin produk 64 | I/O — User I/O (bank 3) |
| Pin produk 65 | I/O — User I/O (bank 3) |
| Pin produk 66 | I/O — User I/O (bank 3) |
| Pin produk 67 | I/O — User I/O (bank 3) |
| Pin produk 68 | I/O — User I/O (bank 3) |
| Pin produk 69 | I/O — User I/O (bank 3) |
| Pin produk 70 | I/O — User I/O (bank 3) |
| Pin produk 71 | I/O — User I/O (bank 3) |
| Pin produk 72 | I/O — User I/O (bank 3) |
| Pin produk 73 | GND — Ground |
| Pin produk 74 | nCONFIG — Configuration control (active-low reset) |
| Pin produk 75 | nSTATUS — Configuration status (active-low) |
| Pin produk 76 | CONF_DONE — Configuration complete (active-high) |
| Pin produk 77 | DCLK — Configuration clock input |
| Pin produk 78 | DATA0 — Configuration data input |
| Pin produk 79 | TCK — JTAG test clock |
| Pin produk 80 | TMS — JTAG test mode select |
| Pin produk 81 | TDI — JTAG test data input |
| Pin produk 82 | TDO — JTAG test data output |
| Pin produk 83 | I/O — User I/O (bank 4) |
| Pin produk 84 | I/O — User I/O (bank 4) |
| Pin produk 85 | I/O — User I/O (bank 4) |
| Pin produk 86 | I/O — User I/O (bank 4) |
| Pin produk 87 | I/O — User I/O (bank 4) |
| Pin produk 88 | I/O — User I/O (bank 4) |
| Pin produk 89 | I/O — User I/O (bank 4) |
| Pin produk 90 | I/O — User I/O (bank 4) |
| Pin produk 91 | I/O — User I/O (bank 4) |
| Pin produk 92 | I/O — User I/O (bank 4) |
| Pin produk 93 | I/O — User I/O (bank 4) |
| Pin produk 94 | I/O — User I/O (bank 4) |
| Pin produk 95 | VCCIO4 — I/O bank 4 supply voltage |
| Pin produk 96 | I/O — User I/O (bank 4) |
| Pin produk 97 | I/O — User I/O (bank 4) |
| Pin produk 98 | I/O — User I/O (bank 4) |
| Pin produk 99 | I/O — User I/O (bank 4) |
| Pin produk 100 | I/O — User I/O (bank 4) |
| Pin produk 101 | I/O — User I/O (bank 4) |
| Pin produk 102 | I/O — User I/O (bank 4) |
| Pin produk 103 | I/O — User I/O (bank 4) |
| Pin produk 104 | I/O — User I/O (bank 4) |
| Pin produk 105 | I/O — User I/O (bank 4) |
| Pin produk 106 | I/O — User I/O (bank 4) |
| Pin produk 107 | GND — Ground |
| Pin produk 108 | I/O — User I/O (bank 5) |
| Pin produk 109 | I/O — User I/O (bank 5) |
| Pin produk 110 | I/O — User I/O (bank 5) |
| Pin produk 111 | I/O — User I/O (bank 5) |
| Pin produk 112 | I/O — User I/O (bank 5) |
| Pin produk 113 | I/O — User I/O (bank 5) |
| Pin produk 114 | I/O — User I/O (bank 5) |
| Pin produk 115 | I/O — User I/O (bank 5) |
| Pin produk 116 | I/O — User I/O (bank 5) |
| Pin produk 117 | I/O — User I/O (bank 5) |
| Pin produk 118 | I/O — User I/O (bank 5) |
| Pin produk 119 | I/O — User I/O (bank 5) |
| Pin produk 120 | I/O — User I/O (bank 5) |
| Pin produk 121 | VCCIO5 — I/O bank 5 supply voltage |
| Pin produk 122 | I/O — User I/O (bank 5) |
| Pin produk 123 | I/O — User I/O (bank 5) |
| Pin produk 124 | I/O — User I/O (bank 5) |
| Pin produk 125 | I/O — User I/O (bank 5) |
| Pin produk 126 | I/O — User I/O (bank 5) |
| Pin produk 127 | I/O — User I/O (bank 5) |
| Pin produk 128 | I/O — User I/O (bank 5) |
| Pin produk 129 | I/O — User I/O (bank 5) |
| Pin produk 130 | I/O — User I/O (bank 5) |
| Pin produk 131 | I/O — User I/O (bank 5) |
| Pin produk 132 | I/O — User I/O (bank 5) |
| Pin produk 133 | GND — Ground |
| Pin produk 134 | I/O — User I/O (bank 6) |
| Pin produk 135 | I/O — User I/O (bank 6) |
| Pin produk 136 | I/O — User I/O (bank 6) |
| Pin produk 137 | I/O — User I/O (bank 6) |
| Pin produk 138 | I/O — User I/O (bank 6) |
| Pin produk 139 | I/O — User I/O (bank 6) |
| Pin produk 140 | I/O — User I/O (bank 6) |
| Pin produk 141 | I/O — User I/O (bank 6) |
| Pin produk 142 | I/O — User I/O (bank 6) |
| Pin produk 143 | I/O — User I/O (bank 6) |
| Pin produk 144 | I/O — User I/O (bank 6) |
| Pin produk 145 | I/O — User I/O (bank 6) |
| Pin produk 146 | I/O — User I/O (bank 6) |
| Pin produk 147 | VCCIO6 — I/O bank 6 supply voltage |
| Pin produk 148 | I/O — User I/O (bank 6) |
| Pin produk 149 | I/O — User I/O (bank 6) |
| Pin produk 150 | I/O — User I/O (bank 6) |
| Pin produk 151 | I/O — User I/O (bank 6) |
| Pin produk 152 | I/O — User I/O (bank 6) |
| Pin produk 153 | I/O — User I/O (bank 6) |
| Pin produk 154 | I/O — User I/O (bank 6) |
| Pin produk 155 | I/O — User I/O (bank 6) |
| Pin produk 156 | I/O — User I/O (bank 6) |
| Pin produk 157 | I/O — User I/O (bank 6) |
| Pin produk 158 | I/O — User I/O (bank 6) |
| Pin produk 159 | GND — Ground |
| Pin produk 160 | I/O — User I/O (bank 7) |
| Pin produk 161 | I/O — User I/O (bank 7) |
| Pin produk 162 | I/O — User I/O (bank 7) |
| Pin produk 163 | I/O — User I/O (bank 7) |
| Pin produk 164 | I/O — User I/O (bank 7) |
| Pin produk 165 | I/O — User I/O (bank 7) |
| Pin produk 166 | I/O — User I/O (bank 7) |
| Pin produk 167 | I/O — User I/O (bank 7) |
| Pin produk 168 | I/O — User I/O (bank 7) |
| Pin produk 169 | I/O — User I/O (bank 7) |
| Pin produk 170 | I/O — User I/O (bank 7) |
| Pin produk 171 | I/O — User I/O (bank 7) |
| Pin produk 172 | VCCIO7 — I/O bank 7 supply voltage |
| Pin produk 173 | I/O — User I/O (bank 7) |
| Pin produk 174 | I/O — User I/O (bank 7) |
| Pin produk 175 | I/O — User I/O (bank 7) |
| Pin produk 176 | I/O — User I/O (bank 7) |
| Pin produk 177 | I/O — User I/O (bank 7) |
| Pin produk 178 | I/O — User I/O (bank 7) |
| Pin produk 179 | I/O — User I/O (bank 7) |
| Pin produk 180 | I/O — User I/O (bank 7) |
| Pin produk 181 | I/O — User I/O (bank 7) |
| Pin produk 182 | I/O — User I/O (bank 7) |
| Pin produk 183 | I/O — User I/O (bank 7) |
| Pin produk 184 | GND — Ground |
| Pin produk 185 | I/O — User I/O (bank 8) |
| Pin produk 186 | I/O — User I/O (bank 8) |
| Pin produk 187 | I/O — User I/O (bank 8) |
| Pin produk 188 | I/O — User I/O (bank 8) |
| Pin produk 189 | I/O — User I/O (bank 8) |
| Pin produk 190 | I/O — User I/O (bank 8) |
| Pin produk 191 | I/O — User I/O (bank 8) |
| Pin produk 192 | I/O — User I/O (bank 8) |
| Pin produk 193 | I/O — User I/O (bank 8) |
| Pin produk 194 | I/O — User I/O (bank 8) |
| Pin produk 195 | I/O — User I/O (bank 8) |
| Pin produk 196 | I/O — User I/O (bank 8) |
| Pin produk 197 | VCCIO8 — I/O bank 8 supply voltage |
| Pin produk 198 | I/O — User I/O (bank 8) |
| Pin produk 199 | I/O — User I/O (bank 8) |
| Pin produk 200 | I/O — User I/O (bank 8) |
| Pin produk 201 | I/O — User I/O (bank 8) |
| Pin produk 202 | I/O — User I/O (bank 8) |
| Pin produk 203 | I/O — User I/O (bank 8) |
| Pin produk 204 | I/O — User I/O (bank 8) |
| Pin produk 205 | I/O — User I/O (bank 8) |
| Pin produk 206 | I/O — User I/O (bank 8) |
| Pin produk 207 | I/O — User I/O (bank 8) |
| Pin produk 208 | GND — Ground |
Aplikasi Umum
EPF6016QI208-3N cocok untuk 6 aplikasis: Legacy Industrial Bus Bridge, ASIC Prototyping Platform, Glue Logic Consolidation, Communication Protocol Bridging, Machine Control State Machines, Educational Logic Design Platform.
Legacy Industrial Bus Bridge
The EPF6016QI208-3N's 16,000 gates and 171 user I/Os make it well-suited to legacy industrial bus-bridge applications, including ISA-to-PCI bridges and parallel-to-serial protocol converters. Its 5V-tolerant I/O banks interface directly to 5V backplanes common in factory automation, eliminating level shifters. With 132 LABs and 1,320 logic elements, the device can implement a full parallel-to-serial bridge with state-machine control and FIFO buffering on a single chip. The 208-PQFP industrial-grade package supports 0C to +85C operating environments typical of factory floors.
Direkomendasikan
ASIC Prototyping Platform
The EPF6016QI208-3N is widely used as an ASIC prototyping vehicle for low-to-mid density designs. Its 0.42 µm CMOS process matches the gate density and timing characteristics of mid-1990s ASIC technology, enabling accurate pre-silicon verification. The SRAM-based configuration allows rapid design iteration without NRE charges, and the 125 MHz internal frequency supports realistic clock-domain emulation. Engineers port VHDL/Verilog RTL from the ASIC target, validate functional behavior, then migrate to the ASIC foundry once verified.
Direkomendasikan
Glue Logic Consolidation
The EPF6016QI208-3N replaces dozens of discrete 74-series TTL logic chips by consolidating address decoding, bus arbitration, and chip-select generation onto a single programmable device. Its 1,320 LEs can absorb the equivalent of 30-50 discrete SSI/MSI logic packages, dramatically reducing PCB area and BOM cost. The 5V-tolerant I/Os and 208-PQFP package footprint are direct retrofits for legacy TTL designs. Configuration is one-time via serial EPROM, eliminating the need for boot code or processor intervention.
Direkomendasikan
Communication Protocol Bridging
The EPF6016QI208-3N implements UART-to-SPI, SPI-to-I2C, and parallel-to-serial protocol bridges for embedded system integration. With 16K gates and 171 I/Os, multiple protocol converters can coexist on a single device with shared address decoding and interrupt logic. The industrial-grade temperature range suits outdoor telecom equipment, while the 5V I/O tolerance simplifies interface to legacy microcontrollers. The 125 MHz internal frequency easily handles standard UART rates up to 921.6 kbaud and SPI clocks up to 25 MHz.
Direkomendasikan
Machine Control State Machines
The EPF6016QI208-3N serves as the central sequencer in CNC machines, conveyor controllers, and packaging equipment, implementing complex multi-state control logic that would otherwise require a microcontroller or custom state-machine IC. Its 132 LABs and 1,320 LEs provide ample capacity for stepper/servo control loops, sensor debouncing, safety interlocks, and HMI interface logic. The 171 I/Os accommodate encoder inputs, limit switches, relay drivers, and operator-panel LEDs without external muxing.
Direkomendasikan
Educational Logic Design Platform
The EPF6016QI208-3N is widely adopted in university digital-logic courses as a teaching vehicle for VHDL/Verilog design, FPGA configuration flows, and timing analysis. Its manageable 16K-gate capacity allows students to focus on architectural learning rather than resource management. The 208-PQFP package on development boards provides accessible probing points for laboratory exercises. Legacy MAX+PLUS II design software remains freely available, supporting a long-tail educational ecosystem that modern Quartus Prime has not displaced.
Direkomendasikan
Ringkasan Produk Direkomendasikan
Data referensi engineering untuk EPF6016QI208-3N — pembandingan, panduan desain, dan informasi konformitas.
Panduan Pemilihan
Pembandingan dengan Alternatif
| Parameter Umum | Produk Ini | EPF6016QI208-3 | EPF6016QC208-3N | EPF6016QC208-3 | EPF6016AQC208-3N | EPF6016AQC208-3 | EPF6016AQC208-2N |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 208-PQFP / 208-BFQFP | 208-PQFP - same | 208-PQFP - same | 208-PQFP - same | 208-PQFP - same | 208-PQFP - same | 208-PQFP - same |
| Usable Gates | 16,000 | 16,000 | 16,000 | 16,000 | 16,000 | 16,000 | 16,000 |
| Logic Elements | 1,320 | 1,320 | 1,320 | 1,320 | 1,320 | 1,320 | 1,320 |
| User I/Os | 171 | 171 | 171 | 171 | 171 | 171 | 171 |
| Speed Grade | -3 | -3 | -3 | -3 | -3 (A-speed) | -3 (A-speed) | -2 (faster than -3) |
| Operating Temperature | 0C to +85C (Industrial) | 0C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Lead-Free (RoHS) | Yes (N suffix) | No (leaded) | Yes (N suffix) | No (leaded) | Yes (N suffix) | No (leaded) | Yes (N suffix) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Diferensiator Kunci
- Industrial temperature grade with lead-free finish (vsEPF6016QC208-3N)
- Lead-free termination for RoHS compliance (vsEPF6016QI208-3)
- Balanced density at 16K gates (vsEPF6016AQC208-2N)
Catatan Desain
The EPF6016QI208-3N requires a stable 5.0V VCCINT supply with ±5% tolerance for the core logic. Decouple VCCINT with one 100 µF bulk capacitor plus four 0.1 µF ceramic capacitors distributed around the package perimeter. Each VCCIO bank (banks 1-8) must be powered from a single rail - mixing 5V and 3.3V on the same bank is forbidden per the FLEX 6000 datasheet. Estimated: ICCINT quiescent current ~5 mA, ICCIO per bank ~10 mA at 10 MHz toggle rate.
The 208-PQFP package has 0.5 mm pitch gull-wing leads and is suitable for 4-layer or 6-layer PCB designs. Provide a continuous ground plane directly under the device to minimize inductance in power/ground paths. Keep all 5V and 3.3V supply traces at least 2 mm wide and route configuration signals (DCLK, DATA0, nCONFIG, nSTATUS, CONF_DONE) on inner layers with ground shielding to avoid noise coupling during power-up configuration.
Do not attempt to use modern Quartus Prime (15.0+) to compile FLEX 6000 designs - support was removed after Quartus II 13.0sp1. Use Altera MAX+PLUS II baseline 10.2 or Quartus II 13.0sp1 for design entry. Verify JTAG chain integrity before configuration - a missing TCK pull-up or incorrect BSDL file will prevent successful configuration. Do not exceed 25 MHz on the DCLK pin during passive serial configuration, as this violates the FLEX 6000 datasheet AC specification.
Differential pair routing is not natively supported on FLEX 6000 I/O; if your design requires LVDS or similar signaling, route traces as tightly-coupled 50 ohm microstrip with matched lengths (±10 mils) and use external LVDS transceivers. Place the configuration EPROM within 6 inches of the FPGA DCLK/DATA0 pins to minimize signal degradation during configuration loading. Add a 1 kΩ pull-up to nCONFIG and a 10 kΩ pull-up to nSTATUS.
Informasi Konformitas
RoHS compliant per the 'N' suffix in the part number (matte-tin Pb-free finish). Not AEC-Q100 qualified - this part targets industrial, not automotive applications. Halogen-free status not specified in available data.
