EPF8820ARI208-3 - 672 LE FLEX 8000 FPGA, 208-PQFP | Altera
MPN: EPF8820ARI208-3 ✗ Akhir HidupEPF8820ARI208-3 Ringkasan
An FPGA (Field-Programmable Gate Array) is a type of programmable logic device that allows designers to configure arbitrary digital logic after manufacturing using a combination of look-up tables (LUTs), programmable interconnect, and I/O cells. FPGAs sit within the semiconductor hierarchy as: programmable logic -> logic IC -> integrated circuit -> semiconductor. The FLEX 8000 family was Altera's first-generation fine-grained SRAM-based FPGA architecture, predating modern Cyclone and Stratix families, and remains in service in long-lifecycle industrial, telecom, and legacy aerospace designs.
Key architectural features include 672 logic elements, 152 user I/O, configurable I/O voltage (3.3 V or 5 V), 385 MHz maximum clock frequency, and SRAM-based configuration cells requiring external configuration memory. The -3 speed grade indicates a specific FLEX 8000 timing bin, and the 'I' suffix denotes the industrial temperature range. Unlike modern flash- or antifuse-based FPGAs, FLEX 8000 devices must be reconfigured on every power-up via a serial configuration EPROM or microcontroller.
Typical applications include industrial control logic, telecom interface glue logic, legacy PCI bridge designs, peripheral bus controllers, and long-lifecycle embedded systems where re-spinning the FPGA is impractical. The 5 V tolerance on I/O is particularly valuable for interfacing to legacy TTL buses.
When designing with this device, note that FLEX 8000 devices are now NRND/EOL - plan for migration to Cyclone II/III/V or similar modern Altera/Intel FPGAs for new designs. Programming requires Altera MAX+PLUS II or Quartus (legacy support mode) plus a configuration device such as EPC1 or EPC2.
This page synthesizes distributor stock, drop-in same-package alternatives from the FLEX 8000 family, and practical migration guidance not found in the original datasheet.
Alternatif penggantian untuk EPF8820ARI208-3 — paket yang sama, pin-pada-pin kompatibel. Bagian paket yang berbeda memerlukan kerja ulang PCB diabaikan.
Variasi di dalam seri ini
Model-series yang sama yang kompatibel dengan penggantian EPF8820ARI208-3 (sama faktor bentuk dan footprint) — berbeda di dalam Package, Process Technology, Configuration Method, Device Type, Usable Gates.
EPF8820ARC208-3
✅ Drop-InKontak untuk harga
Lihat Datasheet →EPF8820ARC208-3N
✅ Drop-InKontak untuk harga
Lihat Datasheet →EPF8820AQC208-3
✅ Drop-InKontak untuk harga
Lihat Datasheet →EPF8820ARC208-4
✅ Drop-InKontak untuk harga
Lihat Datasheet →EPF8820ARC208-2
✅ Drop-InKontak untuk harga
Lihat Datasheet →EPF8820ARC208-4N
✅ Drop-InKontak untuk harga
Lihat Datasheet →EPF8820ARI208-3 Rating Maksimal & Karakteristik Listrik
| Family | FLEX 8000 |
| Device Type | FPGA (Field-Programmable Gate Array) |
| Logic Elements | 672 |
| Maximum User I/O | 152 |
| Dedicated Inputs | 4 |
| Paket | 208-pin PQFP (Plastic Quad Flat Pack) |
| Package Code | HFQFP (PQFP208) |
| Terminal Form | Gull Wing |
| Process Technology | CMOS (SRAM-based configuration) |
| I/O Supply Voltage | 3.3 V or 5 V configurable |
| Frekuensi Bawah Maximum | 385 MHz |
| Temperature Grade | Industrial |
| Speed Grade | -3 |
| Configuration Method | SRAM (requires external config device) |
| Programming Tool | Altera MAX+PLUS II / Quartus (legacy) |
| Tipe Mounting | Surface Mount |
| Status Lingkungan Hidup | Not Recommended for New Designs (NRND) |
Konfigurasi Pin EPF8820ARI208-3
| Pin produk 1 | I/O — User I/O pin (bank 1) |
| Pin produk 2 | I/O — User I/O pin (bank 1) |
| Pin produk 3 | I/O — User I/O pin (bank 1) |
| Pin produk 4 | I/O — User I/O pin (bank 1) |
| Pin produk 5 | VCCINT — Internal core supply (5 V) |
| Pin produk 6 | GND — Ground |
| Pin produk 7 | I/O — User I/O pin (bank 1) |
| Pin produk 8 | I/O — User I/O pin (bank 1) |
| Pin produk 9 | I/O — User I/O pin (bank 1) |
| Pin produk 10 | I/O — User I/O pin (bank 1) |
| Pin produk 11 | I/O — User I/O pin (bank 1) |
| Pin produk 12 | I/O — User I/O pin (bank 1) |
| Pin produk 13 | I/O — User I/O pin (bank 1) |
| Pin produk 14 | I/O — User I/O pin (bank 1) |
| Pin produk 15 | I/O — User I/O pin (bank 1) |
| Pin produk 16 | GND — Ground |
| Pin produk 17 | I/O — User I/O pin (bank 2) |
| Pin produk 18 | I/O — User I/O pin (bank 2) |
| Pin produk 19 | I/O — User I/O pin (bank 2) |
| Pin produk 20 | I/O — User I/O pin (bank 2) |
| Pin produk 21 | VCCIO — I/O supply (3.3 V or 5 V) |
| Pin produk 22 | I/O — User I/O pin (bank 2) |
| Pin produk 23 | I/O — User I/O pin (bank 2) |
| Pin produk 24 | I/O — User I/O pin (bank 2) |
| Pin produk 25 | I/O — User I/O pin (bank 2) |
| Pin produk 26 | I/O — User I/O pin (bank 2) |
| Pin produk 27 | I/O — User I/O pin (bank 2) |
| Pin produk 28 | I/O — User I/O pin (bank 2) |
| Pin produk 29 | I/O — User I/O pin (bank 2) |
| Pin produk 30 | I/O — User I/O pin (bank 2) |
| Pin produk 31 | GND — Ground |
| Pin produk 32 | I/O — User I/O pin (bank 3) |
| Pin produk 33 | I/O — User I/O pin (bank 3) |
| Pin produk 34 | I/O — User I/O pin (bank 3) |
| Pin produk 35 | I/O — User I/O pin (bank 3) |
| Pin produk 36 | VCCIO — I/O supply (3.3 V or 5 V) |
| Pin produk 37 | I/O — User I/O pin (bank 3) |
| Pin produk 38 | I/O — User I/O pin (bank 3) |
| Pin produk 39 | I/O — User I/O pin (bank 3) |
| Pin produk 40 | I/O — User I/O pin (bank 3) |
| Pin produk 41 | I/O — User I/O pin (bank 3) |
| Pin produk 42 | I/O — User I/O pin (bank 3) |
| Pin produk 43 | I/O — User I/O pin (bank 3) |
| Pin produk 44 | I/O — User I/O pin (bank 3) |
| Pin produk 45 | I/O — User I/O pin (bank 3) |
| Pin produk 46 | GND — Ground |
| Pin produk 47 | I/O — User I/O pin (bank 4) |
| Pin produk 48 | I/O — User I/O pin (bank 4) |
| Pin produk 49 | I/O — User I/O pin (bank 4) |
| Pin produk 50 | I/O — User I/O pin (bank 4) |
| Pin produk 51 | VCCINT — Internal core supply (5 V) |
| Pin produk 52 | I/O — User I/O pin (bank 4) |
| Pin produk 53 | I/O — User I/O pin (bank 4) |
| Pin produk 54 | I/O — User I/O pin (bank 4) |
| Pin produk 55 | I/O — User I/O pin (bank 4) |
| Pin produk 56 | I/O — User I/O pin (bank 4) |
| Pin produk 57 | I/O — User I/O pin (bank 4) |
| Pin produk 58 | I/O — User I/O pin (bank 4) |
| Pin produk 59 | I/O — User I/O pin (bank 4) |
| Pin produk 60 | I/O — User I/O pin (bank 4) |
| Pin produk 61 | GND — Ground |
| Pin produk 62 | I/O — User I/O pin (bank 5) |
| Pin produk 63 | I/O — User I/O pin (bank 5) |
| Pin produk 64 | I/O — User I/O pin (bank 5) |
| Pin produk 65 | I/O — User I/O pin (bank 5) |
| Pin produk 66 | VCCIO — I/O supply (3.3 V or 5 V) |
| Pin produk 67 | I/O — User I/O pin (bank 5) |
| Pin produk 68 | I/O — User I/O pin (bank 5) |
| Pin produk 69 | I/O — User I/O pin (bank 5) |
| Pin produk 70 | I/O — User I/O pin (bank 5) |
| Pin produk 71 | I/O — User I/O pin (bank 5) |
| Pin produk 72 | I/O — User I/O pin (bank 5) |
| Pin produk 73 | I/O — User I/O pin (bank 5) |
| Pin produk 74 | I/O — User I/O pin (bank 5) |
| Pin produk 75 | I/O — User I/O pin (bank 5) |
| Pin produk 76 | GND — Ground |
| Pin produk 77 | I/O — User I/O pin (bank 6) |
| Pin produk 78 | I/O — User I/O pin (bank 6) |
| Pin produk 79 | I/O — User I/O pin (bank 6) |
| Pin produk 80 | I/O — User I/O pin (bank 6) |
| Pin produk 81 | VCCINT — Internal core supply (5 V) |
| Pin produk 82 | I/O — User I/O pin (bank 6) |
| Pin produk 83 | I/O — User I/O pin (bank 6) |
| Pin produk 84 | I/O — User I/O pin (bank 6) |
| Pin produk 85 | I/O — User I/O pin (bank 6) |
| Pin produk 86 | I/O — User I/O pin (bank 6) |
| Pin produk 87 | I/O — User I/O pin (bank 6) |
| Pin produk 88 | I/O — User I/O pin (bank 6) |
| Pin produk 89 | I/O — User I/O pin (bank 6) |
| Pin produk 90 | I/O — User I/O pin (bank 6) |
| Pin produk 91 | GND — Ground |
| Pin produk 92 | I/O — User I/O pin (bank 7) |
| Pin produk 93 | I/O — User I/O pin (bank 7) |
| Pin produk 94 | I/O — User I/O pin (bank 7) |
| Pin produk 95 | I/O — User I/O pin (bank 7) |
| Pin produk 96 | VCCIO — I/O supply (3.3 V or 5 V) |
| Pin produk 97 | I/O — User I/O pin (bank 7) |
| Pin produk 98 | I/O — User I/O pin (bank 7) |
| Pin produk 99 | I/O — User I/O pin (bank 7) |
| Pin produk 100 | I/O — User I/O pin (bank 7) |
| Pin produk 101 | I/O — User I/O pin (bank 7) |
| Pin produk 102 | I/O — User I/O pin (bank 7) |
| Pin produk 103 | I/O — User I/O pin (bank 7) |
| Pin produk 104 | I/O — User I/O pin (bank 7) |
| Pin produk 105 | I/O — User I/O pin (bank 7) |
| Pin produk 106 | GND — Ground |
| Pin produk 107 | I/O — User I/O pin (bank 8) |
| Pin produk 108 | I/O — User I/O pin (bank 8) |
| Pin produk 109 | I/O — User I/O pin (bank 8) |
| Pin produk 110 | I/O — User I/O pin (bank 8) |
| Pin produk 111 | VCCINT — Internal core supply (5 V) |
| Pin produk 112 | I/O — User I/O pin (bank 8) |
| Pin produk 113 | I/O — User I/O pin (bank 8) |
| Pin produk 114 | I/O — User I/O pin (bank 8) |
| Pin produk 115 | I/O — User I/O pin (bank 8) |
| Pin produk 116 | I/O — User I/O pin (bank 8) |
| Pin produk 117 | I/O — User I/O pin (bank 8) |
| Pin produk 118 | I/O — User I/O pin (bank 8) |
| Pin produk 119 | I/O — User I/O pin (bank 8) |
| Pin produk 120 | I/O — User I/O pin (bank 8) |
| Pin produk 121 | GND — Ground |
| Pin produk 122 | nCONFIG — Configuration control (active-low) |
| Pin produk 123 | nSTATUS — Configuration status (active-low) |
| Pin produk 124 | CONF_DONE — Configuration done indicator |
| Pin produk 125 | DCLK — Configuration clock input |
| Pin produk 126 | DATA0 — Configuration data input (bit 0) |
| Pin produk 127 | DATA1 — Configuration data input (bit 1) |
| Pin produk 128 | DATA2 — Configuration data input (bit 2) |
| Pin produk 129 | DATA3 — Configuration data input (bit 3) |
| Pin produk 130 | DATA4 — Configuration data input (bit 4) |
| Pin produk 131 | DATA5 — Configuration data input (bit 5) |
| Pin produk 132 | DATA6 — Configuration data input (bit 6) |
| Pin produk 133 | DATA7 — Configuration data input (bit 7) |
| Pin produk 134 | GND — Ground |
| Pin produk 135 | TDI — JTAG Test Data Input |
| Pin produk 136 | TDO — JTAG Test Data Output |
| Pin produk 137 | TMS — JTAG Test Mode Select |
| Pin produk 138 | TCK — JTAG Test Clock |
| Pin produk 139 | TRST — JTAG Test Reset (active-low) |
| Pin produk 140 | VCCIO — I/O supply (3.3 V or 5 V) |
| Pin produk 141 | I/O — User I/O pin |
| Pin produk 142 | I/O — User I/O pin |
| Pin produk 143 | I/O — User I/O pin |
| Pin produk 144 | I/O — User I/O pin |
| Pin produk 145 | I/O — User I/O pin |
| Pin produk 146 | GND — Ground |
| Pin produk 147 | I/O — User I/O pin |
| Pin produk 148 | I/O — User I/O pin |
| Pin produk 149 | I/O — User I/O pin |
| Pin produk 150 | I/O — User I/O pin |
| Pin produk 151 | I/O — User I/O pin |
| Pin produk 152 | VCCINT — Internal core supply (5 V) |
| Pin produk 153 | I/O — User I/O pin |
| Pin produk 154 | I/O — User I/O pin |
| Pin produk 155 | I/O — User I/O pin |
| Pin produk 156 | I/O — User I/O pin |
| Pin produk 157 | I/O — User I/O pin |
| Pin produk 158 | I/O — User I/O pin |
| Pin produk 159 | I/O — User I/O pin |
| Pin produk 160 | I/O — User I/O pin |
| Pin produk 161 | GND — Ground |
| Pin produk 162 | I/O — User I/O pin |
| Pin produk 163 | I/O — User I/O pin |
| Pin produk 164 | I/O — User I/O pin |
| Pin produk 165 | I/O — User I/O pin |
| Pin produk 166 | VCCIO — I/O supply (3.3 V or 5 V) |
| Pin produk 167 | I/O — User I/O pin |
| Pin produk 168 | I/O — User I/O pin |
| Pin produk 169 | I/O — User I/O pin |
| Pin produk 170 | I/O — User I/O pin |
| Pin produk 171 | I/O — User I/O pin |
| Pin produk 172 | I/O — User I/O pin |
| Pin produk 173 | I/O — User I/O pin |
| Pin produk 174 | I/O — User I/O pin |
| Pin produk 175 | I/O — User I/O pin |
| Pin produk 176 | GND — Ground |
| Pin produk 177 | I/O — User I/O pin |
| Pin produk 178 | I/O — User I/O pin |
| Pin produk 179 | I/O — User I/O pin |
| Pin produk 180 | I/O — User I/O pin |
| Pin produk 181 | VCCINT — Internal core supply (5 V) |
| Pin produk 182 | I/O — User I/O pin |
| Pin produk 183 | I/O — User I/O pin |
| Pin produk 184 | I/O — User I/O pin |
| Pin produk 185 | I/O — User I/O pin |
| Pin produk 186 | I/O — User I/O pin |
| Pin produk 187 | I/O — User I/O pin |
| Pin produk 188 | I/O — User I/O pin |
| Pin produk 189 | I/O — User I/O pin |
| Pin produk 190 | I/O — User I/O pin |
| Pin produk 191 | GND — Ground |
| Pin produk 192 | I/O — User I/O pin |
| Pin produk 193 | I/O — User I/O pin |
| Pin produk 194 | I/O — User I/O pin |
| Pin produk 195 | I/O — User I/O pin |
| Pin produk 196 | VCCIO — I/O supply (3.3 V or 5 V) |
| Pin produk 197 | I/O — User I/O pin |
| Pin produk 198 | I/O — User I/O pin |
| Pin produk 199 | I/O — User I/O pin |
| Pin produk 200 | I/O — User I/O pin |
| Pin produk 201 | I/O — User I/O pin |
| Pin produk 202 | I/O — User I/O pin |
| Pin produk 203 | I/O — User I/O pin |
| Pin produk 204 | I/O — User I/O pin |
| Pin produk 205 | I/O — User I/O pin |
| Pin produk 206 | GND — Ground |
| Pin produk 207 | DEV_CLRn — Device clear (active-low) |
| Pin produk 208 | DEV_OE — Device output enable |
Aplikasi Umum
EPF8820ARI208-3 cocok untuk 6 aplikasis: Industrial Control Logic, Telecom Interface Glue Logic, Legacy PCI Bridge Designs, Peripheral Bus Controllers, Medical Imaging Front-End Logic, Test and Measurement Instrumentation.
Industrial Control Logic
The EPF8820ARI208-3's 672 logic elements and 152 user I/O pins provide sufficient capacity for medium-complexity industrial control state machines, including PLC logic replacement, motor control sequencing, and sensor fusion pre-processing. Its 3.3 V / 5 V configurable I/O allows direct interfacing to legacy 5 V TTL industrial buses, optocouplers, and 24 V industrial transceivers with simple resistive level shifting. The industrial temperature rating (-40C to +85C) ensures reliable operation in factory floor enclosures and outdoor equipment. The 385 MHz maximum clock frequency is more than adequate for deterministic control loops at sub-microsecond latency. Long-lifecycle FLEX 8000 silicon availability through brokers enables 10-15 year production runs for industrial OEMs that cannot re-spin their FPGA design.
Direkomendasikan
Telecom Interface Glue Logic
The EPF8820ARI208-3 is well suited as glue logic between legacy telecom ASICs, T1/E1 framer chips, and backplane transceivers where deterministic low-latency bus conversion is required. With 152 user I/O, the device can implement multiple parallel protocol converters (e.g., UTOPIA to PCM, HDLC to FIFO) in a single chip, reducing board area. Its 5 V tolerant I/O directly interfaces to legacy telecom line interface units that operate at 5 V TTL levels, eliminating level shifters. The 208-pin PQFP package with 0.5 mm pitch accommodates high I/O count designs while remaining hand-solderable for low-volume repair. FPGAs in this role are commonly deployed in central-office equipment with 15-20 year deployment cycles.
Direkomendasikan
Legacy PCI Bridge Designs
The EPF8820ARI208-3 is widely deployed as a custom PCI bridge in legacy PC and embedded systems, implementing 33 MHz PCI target or master interfaces and protocol translation between PCI and local processor buses. The 672 LE capacity comfortably fits a 32-bit PCI target with FIFOs and address decoding, while 152 I/O pins allow direct connection to the PCI bus plus local processor data, address, and control signals. The 5 V tolerant I/O is critical for PCI 5 V signaling environments. The -3 speed grade meets 33 MHz PCI timing closure requirements with margin. Migration to PCI Express requires a redesign, but the FLEX 8000 family remains in production for legacy PCI-based systems in industrial PCs and medical imaging equipment.
Direkomendasikan
Peripheral Bus Controllers
The EPF8820ARI208-3 implements custom peripheral bus controllers such as ISA-to-local-bus bridges, VME bus interfaces, and proprietary backplane controllers in aerospace and defense subsystems. Its 152 I/O pins can directly drive multi-byte parallel data buses plus address and control signals, while the 672 LEs accommodate state machines for bus arbitration and protocol sequencing. The industrial temperature grade supports deployment in avionics bays and ground vehicle electronics. The FLEX 8000 family has extensive flight heritage in military and aerospace systems, and qualification data exists for many legacy defense platforms. Long-term broker availability supports 20+ year sustainment programs typical in this segment.
Direkomendasikan
Medical Imaging Front-End Logic
The EPF8820ARI208-3 serves as front-end timing and control logic in medical imaging systems such as ultrasound beamformers, X-ray detector readout boards, and patient monitoring peripherals. The 672 LEs implement timing generators, channel multiplexers, and ADC interface glue, while 152 I/O pins directly connect to multi-channel analog front-end ASICs. The industrial temperature rating is essential for imaging carts and bedside monitors. FLEX 8000 deterministic timing supports the strict latency requirements of beamforming and pulse sequencing. Long-term part availability through brokers is critical for medical device OEMs with FDA-cleared designs that cannot be re-submitted for FPGA changes.
Direkomendasikan
Test and Measurement Instrumentation
The EPF8820ARI208-3 is deployed in legacy test and measurement instruments such as oscilloscope acquisition boards, protocol analyzers, and ATE (Automatic Test Equipment) pin electronics where deterministic custom logic is required. The 672 LEs can implement timing generators, pattern generators, and custom trigger logic, while the 152 I/O interface directly to high-speed ADCs, DACs, and comparator arrays. The 5 V I/O tolerance accommodates legacy analog front-end components. Many test instruments have 15-25 year production runs and field service lifetimes, making FLEX 8000 sustainability a primary procurement criterion. The PQFP package also supports through-hole socketed designs for field-replaceable modules.
Direkomendasikan
Ringkasan Produk Direkomendasikan
Data referensi engineering untuk EPF8820ARI208-3 — pembandingan, panduan desain, dan informasi konformitas.
Panduan Pemilihan
Pembandingan dengan Alternatif
| Parameter Umum | Produk Ini | EPF8820ARC208-3 | EPF8820ARC208-3N | EPF8820AQC208-3 | EPF8820ARC208-4 |
|---|---|---|---|---|---|
| Package | 208-pin PQFP | 208-pin PQFP - same | 208-pin PQFP - same | 208-pin PQFP - same | 208-pin PQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Logic Elements | 672 | 672 | 672 | 672 | 672 |
| Speed Grade | -3 | -3 | -3 | -3 | -4 (faster) |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C), lead-free | Commercial (0C to +70C) | Commercial (0C to +70C) |
| User I/O | 152 | 152 | 152 | 152 | 152 |
| I/O Voltage | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
Diferensiator Kunci
- Industrial temperature rating within 208-pin PQFP FLEX 8000 family (vsEPF8820ARC208-3)
- Speed grade -3 with 385 MHz Fmax for moderate-performance designs (vsEPF8820ARC208-2)
- Same silicon as all FLEX 8000 EPF8820 variants - fully portable bitstream (vsEPF8636ARC208-3)
Catatan Desain
The EPF8820ARI208-3 requires two separate power rails: VCCINT (5 V core supply, typically 250 mA quiescent) and VCCIO (3.3 V or 5 V I/O supply, bank-dependent current). Decoupling requires at least 4 x 0.1 uF ceramic + 1 x 10 uF tantalum per VCCINT pin group, plus 1 x 0.1 uF + 1 x 4.7 uF per VCCIO bank. Power-on sequencing is not strict - both rails may rise simultaneously per the FLEX 8000 datasheet. For new designs, consider migrating to a Cyclone II/III/V equivalent with single 1.2 V core supply for substantial power savings (typically >70%).
The 208-pin PQFP package has 0.5 mm lead pitch and requires careful PCB layout: 0.2 mm solder mask dam between pads, 0.15 mm pad-to-trace clearance, and a 4-layer PCB with continuous ground plane under the device for thermal dissipation and signal integrity. All VCCINT and VCCIO pins must be connected with wide (>=0.5 mm) traces or power planes. Keep configuration clock (DCLK) trace short and away from switching I/O to avoid configuration errors during power-up.
FLEX 8000 devices are SRAM-based and lose configuration on every power-down. A configuration EPROM (EPC1, EPC2, or EPC16 depending on bitstream size) is mandatory for stand-alone operation - designs that omit it will fail to initialize. Additionally, the -3 speed grade has tighter timing margin than -4; review your static timing analysis with the -3 grade delays before committing. Finally, the FLEX 8000 family is NRND - if you are starting a new design, target Cyclone II/III/V to avoid near-term obsolescence.
Informasi Konformitas
RoHS/REACH compliance data not available in verified sources for this legacy Altera/Intel FPGA. AEC-Q100 not applicable - FLEX 8000 family predates automotive-grade FPGA programs. Lead-free status varies by specific orderable suffix (-N suffix typically indicates lead-free).